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| 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0073-0401Z Rev.4.01 Nov 14, 2003 DESCRIPTION The 3803/3804 group is the 8-bit microcomputer based on the 740 family core technology. The 3803/3804 group is designed for household products, office automation equipment, and controlling systems that require analog signal processing, including the A-D converter and D-A converters. The 3804 group is the version of the 3803 group to which an I2CBUS control function has been added. FEATURES qBasic machine-language instructions ...................................... 71 qMinimum instruction execution time ................................ 0.24 s (at 16.8 MHz oscillation frequency) qMemory size ROM ............................................................... 16 K to 60 K bytes RAM ................................................................. 640 to 2048 bytes qProgrammable input/output ports ............................................ 56 qSoftware pull-up resistors ................................................. Built-in qInterrupts 21 sources, 16 vectors ............................................... 3803 group (external 8, internal 12, software 1) 23 sources, 16 vectors ............................................... 3804 group (external 9, internal 13, software 1) qTimers ........................................................................... 16-bit 1 8-bit 4 (with 8-bit prescaler) qWatchdog timer ............................................................ 16-bit 1 qSerial I/O ...................... 8-bit 2 (UART or Clock-synchronized) 8-bit 1 (Clock-synchronized) qPWM ............................................ 8-bit 1 (with 8-bit prescaler) qI2C-BUS interface (3804 group only) ........................... 1 channel qA-D converter ............................................. 10-bit 16 channels (8-bit reading enabled) qD-A converter ................................................. 8-bit 2 channels qLED direct drive port .................................................................. 8 qClock generating circuit ..................................... Built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) qPower source voltage In high-, middle-speed mode At 16.8 MHz oscillation frequency ............................ 4.5 to 5.5 V At 12.5 MHz oscillation frequency ............................ 4.0 to 5.5 V At 8.38 MHz oscillation frequency) ........................ 2.7 to 5.5 V In low-speed mode At 32 kHz oscillation frequency .............................. 2.7 to 5.5 V ( This value of flash memory version is 4.0 to 5.5 V.) qPower dissipation In high-speed mode ................................................ 60 mW (typ.) (at 16.8 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode ................................................... 60 W (typ.) (at 32 kHz oscillation frequency, at 3 V power source voltage) qOperating temperature range .................................... -20 to 85C qPackages SP .................................................. 64P4B (64-pin 750 mil SDIP) FP ....................................... 64P6N-A (64-pin 14 14 mm QFP) HP ..................................... 64P6Q-A (64-pin 10 10 mm LQFP) Rev.4.01 Nov 14, 2003 page 1 of 136 3803/3804 Group PIN CONFIGURATION (TOP VIEW) P10/INT41 P02/AN10 P03/AN11 P06/AN14 P05/AN13 P00/AN8 P07/AN15 P11/INT01 P04/AN12 P01/AN9 P12 P13 P14 P15 35 P16 34 P17 33 47 44 42 41 48 46 43 38 37 45 40 39 36 P37/SRDY3 P36/SCLK3 P35/TXD3 P34/RXD3 P33 P32 P31/DA2 P30/DA1 VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 13 14 10 11 15 12 16 2 1 3 5 6 4 7 8 9 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) VSS XOUT XIN P40/INT40/XCOUT P41/INT00/XCIN RESET CNVSS VPP P42/INT1 M38039FFFP/HP M38037M8-XXXFP/HP P51/SOUT2 P54/CNTR0 P55/CNTR1 P47/SRDY1/CNTR2 P53/SRDY2 P52/SCLK2 P46/SCLK1 P57/INT3 P56/PWM P44/RXD1 P45/TXD1 P43/INT2 P61/AN1 P62/AN2 P60/AN0 P50/SIN2 : Flash memory version Package type : 64P6N-A/64P6Q-A Fig. 1 3803 group pin configuration PIN CONFIGURATION (TOP VIEW) VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1/CNTR2 P46/SCLK1 P45/TXD1 P44/RXD1 P43/INT2 P42/INT1 VPP CNVSS RESET P41/INT00/XCIN P40/INT40/XCOUT XIN XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30/DA1 P31/DA2 P32 P33 P34/RXD3 P35/TXD3 P36/SCLK3 P37/SRDY3 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 P10/INT41 P11/INT01 P12 P13 P14 P15 P16 P17 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) : Flash memory version Package type : 64P4B Fig. 2 3803 group pin configuration M38039FFSP M38037M8-XXXSP Rev.4.01 Nov 14, 2003 page 2 of 136 3803/3804 Group PIN CONFIGURATION (TOP VIEW) P10/INT41 P11/INT01 P04/AN12 P05/AN13 P06/AN14 P03/AN11 P02/AN10 P07/AN15 P00/AN8 P01/AN9 P12 P13 P14 P15 35 P16 34 P17 33 46 45 43 48 47 44 42 41 40 39 38 37 36 P37/SRDY3 P36/SCLK3 P35/TXD3 P34/RXD3 P33/SCL P32/SDA P31/DA2 P30/DA1 VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 11 13 14 12 15 16 1 2 3 4 6 7 5 8 9 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) VSS XOUT XIN P40/INT40/XCOUT P41/INT00/XCIN RESET CNVSS VPP P42/INT1 M38049FFFP/HP M38047M8-XXXFP/HP P57/INT3 P53/SRDY2 P61/AN1 P55/CNTR1 P47/SRDY1/CNTR2 P46/SCLK1 P45/TXD1 P54/CNTR0 P51/SOUT2 P50/SIN2 P52/SCLK2 P56/PWM P44/RXD1 P43/INT2 P62/AN2 P60/AN0 : Flash memory version Package type : 64P6N-A/64P6Q-A Fig. 3 3804 group pin configuration PIN CONFIGURATION (TOP VIEW) VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1/CNTR2 P46/SCLK1 P45/TXD1 P44/RXD1 P43/INT2 P42/INT1 VPP CNVSS RESET P41/INT00/XCIN P40/INT40/XCOUT XIN XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30/DA1 P31/DA2 P32/SDA P33/SCL P34/RXD3 P35/TXD3 P36/SCLK3 P37/SRDY3 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 P10/INT41 P11/INT01 P12 P13 P14 P15 P16 P17 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) : Flash memory version Package type : 64P4B Fig. 4 3804 group pin configuration M38049FFSP M38047M8-XXXSP Rev.4.01 Nov 14, 2003 page 3 of 136 Rev.4.01 Reset input FUNCTIONAL BLOCK DIAGRAM (Package: 64P4B) Clock Clock Sub-clock Sub-clock input output input output 3803/3804 Group X IN X OUT X CIN X COUT V SS V CC RESET CNVSS 26 27 1 32 FUNCTIONAL BLOCK Fig. 5 3803 group functional block diagram Nov 14, 2003 Data bus CPU Timer 1 (8) A X Y Prescaler X (8) Prescaler 12 (8) 30 31 28 29 page 4 of 136 RAM ROM S CNTR0 Prescaler Y (8) Clock generating circuit Timer 2 (8) Timer X (8) Timer Y (8) PC H PS PCL CNTR1 Timer Z (16) CNTR2 A-D converter (10) PWM(8) SI/O2(8) SI/O1(8) D-A D-A converter converter 2 (8) 1 (8) SI/O3(8) INT3 INT00 INT1 INT2 INT40 INT01 INT41 P6(8) P5(8) P4(8) P3(8) P2(8) P1(8) P0(8) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 28 29 57 58 59 60 61 62 63 64 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 VREF AVSS I/O port P6 I/O port P5 I/O port P4 I/O port P3 I/O port P2 (LED drive) I/O port P1 I/O port P0 Rev.4.01 Reset input FUNCTIONAL BLOCK DIAGRAM (Package: 64P4B) Clock Clock Sub-clock Sub-clock input output input output X IN X OUT X CIN X COUT V SS V CC RESET CNVSS 26 27 1 32 29 3803/3804 Group 30 31 28 Fig. 6 3804 group functional block diagram Data bus Nov 14, 2003 CPU Timer 1 (8) A X Y Prescaler X (8) Prescaler 12 (8) Clock generating circuit page 5 of 136 RAM ROM S CNTR0 Prescaler Y (8) Timer 2 (8) Timer X (8) Timer Y (8) PC H PS PCL CNTR1 Timer Z (16) CNTR2 A-D converter (10) PWM(8) SI/O2(8) SI/O1(8) D-A D-A converter converter 2 (8) 1 (8) SI/O3(8) I 2C INT3 INT00 INT1 INT2 INT40 INT01 INT41 P6(8) P5(8) P4(8) P3(8) P2(8) P1(8) P0(8) 23 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 28 29 57 58 59 60 61 62 63 64 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 VREF AVSS I/O port P6 I/O port P5 I/O port P4 I/O port P3 I/O port P2 (LED drive) I/O port P1 I/O port P0 3803/3804 Group PIN DESCRIPTION Table 1 Pin description (3803 group) Pin VCC, VSS CNVSS Name Power source CNVSS input Functions *Apply voltage of 2.7 V - 5.5 V to Vcc, and 0 V to Vss. *In the flash memory version, apply voltage of 4.0 V - 5.5 V to Vcc, and 0 V to Vss *This pin controls the operation mode of the chip. *Normally connected to VSS. *In the flash memory version, this becomes VPP power source input pin. VREF AVSS RESET XIN Reference voltage Analog power source Reset input Clock input Clock output I/O port P0 I/O port P1 *Reference voltage input pin for A-D and D-A converters. *Analog power source input pin for A-D and D-A converters. *Connect to VSS. *Reset input pin for active "L". *Input and output pins for the clock generating circuit. *Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. *When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. *A-D converter input pin *8-bit CMOS I/O port. *I/O direction register allows each pin to be individually *Interrupt input pin programmed as either input or output. *CMOS compatible input level. *CMOS 3-state output structure. I/O port P2 I/O port P3 *Pull-up control is enabled in a bit unit. *P20-P27 are enabled to output large current for LED drive. P30/DA1 P31/DA2 P32, P33 P34/RxD3 P35/TxD3 P36/SCLK3 P37/SRDY3 P40/INT40/ XCOUT P41/INT00/ XCIN P42/INT1 P43/INT2 P44/RxD1 P45/TxD1 P46/SCLK1 P47/SRDY1 /CNTR2 P50/SIN2 P51/SOUT2 P52/SCLK2 P53/SRDY2 P54/CNTR0 P55/CNTR1 P56/PWM P57/INT3 P60/AN0- P67/AN7 I/O port P6 I/O port P5 *8-bit CMOS I/O port. *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level. *CMOS 3-state output structure. *Pull-up control is enabled in a bit unit. *Timer X function pin *Timer Y function pin *PWM output pin *Interrupt input pin *A-D converter input pin *Serial I/O1, timer Z function pin *Serial I/O2 function pin I/O port P4 *8-bit CMOS I/O port. *I/O direction register allows each pin to be individually programmed as either input or output. *P30, P31, P34-P37 are CMOS 3-state output structure. *Serial I/O3 function pin *P32, P33 are N-channel open-drain output structure. *Pull-up control of P30, P31, P34-P37 is enabled in a bit unit. *8-bit CMOS I/O port. *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level. *CMOS 3-state output structure. *Pull-up control is enabled in a bit unit. *Serial I/O1 function pin *Interrupt input pin *Interrupt input pin *Sub-clock generating I/O pin (resonator connected) *D-A converter input pin Function except a port function XOUT P00/AN8- P07/AN15 P10/INT41 P11/INT01 P12-P17 P20-P27 Rev.4.01 Nov 14, 2003 page 6 of 136 3803/3804 Group Table 2 Pin description (3804 group) Pin VCC, VSS CNVSS Name Power source CNVSS input Functions *Apply voltage of 2.7 V - 5.5 V to Vcc, and 0 V to Vss. *In the flash memory version, apply voltage of 4.0 V - 5.5 V to Vcc, and 0 V to Vss *This pin controls the operation mode of the chip. *Normally connected to VSS. *In the flash memory version, this becomes VPP power source input pin. VREF AVSS RESET XIN XOUT P00/AN8- P07/AN15 P10/INT41 P11/INT01 P12-P17 P20-P27 I/O port P2 Reference voltage Analog power source Reset input Clock input Clock output I/O port P0 I/O port P1 *Reference voltage input pin for A-D and D-A converters. *Analog power source input pin for A-D and D-A converters. *Connect to VSS. *Reset input pin for active "L". *Input and output pins for the clock generating circuit. *Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. *When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. *A-D converter input pin *8-bit CMOS I/O port. *I/O direction register allows each pin to be individually *Interrupt input pin programmed as either input or output. *CMOS compatible input level. *CMOS 3-state output structure. *Pull-up control is enabled in a bit unit. *P20-P27 are enabled to output large current for LED drive. P30/DA1 P31/DA2 P32/SDA P33/SCL P34/RxD3 P35/TxD3 P36/SCLK3 P37/SRDY3 P40/INT40/ XCOUT P41/INT00/ XCIN P42/INT1 P43/INT2 P44/RxD1 P45/TxD1 P46/SCLK1 P47/SRDY1 /CNTR2 P50/SIN2 P51/SOUT2 P52/SCLK2 P53/SRDY2 P54/CNTR0 P55/CNTR1 P56/PWM P57/INT3 P60/AN0- P67/AN7 I/O port P6 I/O port P5 *8-bit CMOS I/O port. *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level. *CMOS 3-state output structure. *Pull-up control is enabled in a bit unit. *Timer X function pin *Timer Y function pin *PWM output pin *Interrupt input pin *A-D converter input pin *Serial I/O1, timer Z function pin *Serial I/O2 function pin I/O port P4 I/O port P3 *8-bit CMOS I/O port. *I/O direction register allows each pin to be individually programmed as either input or output. *D-A converter input pin Function except a port function *I2C-BUS interface function pins *P32 to P33 can be switched between CMOS compatible input level or SMBUS input level in the I2C-BUS *Serial I/O3 function pin interface function. *P30, P31, P34-P37 are CMOS 3-state output structure. *P32, P33 are N-channel open-drain output structure. *Pull-up control of P30, P31, P34-P37 is enabled in a bit unit. *8-bit CMOS I/O port. *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level. *CMOS 3-state output structure. *Pull-up control is enabled in a bit unit. *Serial I/O1 function pin *Interrupt input pin *Interrupt input pin *Sub-clock generating I/O pin (resonator connected) Rev.4.01 Nov 14, 2003 page 7 of 136 3803/3804 Group PART NUMBERING Product name M3803 7 M 8 - XXX SP Package type SP : 64P4B FP : 64P6N-A HP : 64P6Q-A ROM number Omitted in the flash memory version. - : standard Omitted in the flash memory version. ROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used as a user's ROM area. However, they can be programmed or erased in the flash memory version, so that the users can use them. 9 : 36864 bytes A : 40960 bytes B : 45056 bytes C : 49152 bytes D : 53248 bytes E : 57344 bytes F : 61440 bytes Memory type M : Mask ROM version F : Flash memory version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes Group 3803: 3803 group 3804: 3804 group Fig. 7 Part numbering Rev.4.01 Nov 14, 2003 page 8 of 136 3803/3804 Group GROUP EXPANSION GROUP EXPANSION Renesas plans to expand the 3803/3804 group as follows. Packages 64P4B ......................................... 64-pin shrink plastic-molded DIP 64P6N-A .................................... 0.8 mm-pitch plastic molded QFP 64P6Q-A .................................. 0.5 mm-pitch plastic molded LQFP Memory Type Support for mask ROM and flash memory versions. Memory Size Flash memory size ......................................................... 60 K bytes Mask ROM size ................................................. 16 K to 60 K bytes RAM size ............................................................ 640 to 2048 bytes Memory Expansion Plan ROM size (bytes) ROM exteranal 60K : Mass production As of Nov. 2003 M38039MF, M38049MF M38039FP, M38049FF 48K 32K 28K 24K 20K 16K 12K 8K M38039MC M38049MC M38037M8 M38047M8 M38037M6 M38047M6 M38034M4 M38044M4 384 512 640 768 896 1024 1152 1280 1408 1536 2048 3072 4032 RAM size (bytes) Fig. 8 Memory expansion plan Rev.4.01 Nov 14, 2003 page 9 of 136 3803/3804 Group Currently planning products are listed below. Table 3 Support products Product name M38034M4-XXXSP M38034M4-XXXFP M38034M4-XXXHP M38044M4-XXXSP M38044M4-XXXFP M38044M4-XXXHP M38037M6-XXXSP M38037M6-XXXFP M38037M6-XXXHP M38047M6-XXXSP M38047M6-XXXFP M38047M6-XXXHP M38037M8-XXXSP M38037M8-XXXFP M38037M8-XXXHP M38047M8-XXXSP M38047M8-XXXFP M38047M8-XXXHP M38039MC-XXXSP M38039MC-XXXFP M38039MC-XXXHP M38049MC-XXXSP M38049MC-XXXFP M38049MC-XXXHP M38039MF-XXXSP M38039MF-XXXFP M38039MF-XXXHP M38049MF-XXXSP M38049MF-XXXFP M38049MF-XXXHP M38039FFSP M38039FFFP M38039FFHP M38049FFSP M38049FFFP M38049FFHP 61440 2048 2048 49152 (49022) 2048 32768 (32638) 1024 24576 (24446) 1024 16384 (16254) 640 ROM size (bytes) ROM size for User in ( ) RAM size (bytes) Package 64P4B 64P6N-A 64P6Q-A 64P4B 64P6N-A 64P6Q-A 64P4B 64P6N-A 64P6Q-A 64P4B 64P6N-A 64P6Q-A 64P4B 64P6N-A 64P6Q-A 64P4B 64P6N-A 64P6Q-A 64P4B 64P6N-A 64P6Q-A 64P4B 64P6N-A 64P6Q-A 64P4B 64P6N-A 61440 (61310) 64P6Q-A 64P4B 64P6N-A 64P6Q-A 64P4B 64P6N-A 64P6Q-A 64P4B 64P6N-A 64P6Q-A Flash memory version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Remarks As of Nov. 2003 Mask ROM version Rev.4.01 Nov 14, 2003 page 10 of 136 3803/3804 Group FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 3803/3804 group uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used. [Stack Pointer (S)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is "0" , the high-order 8 bits becomes "0016". If the stack page selection bit is "1", the high-order 8 bits becomes "0116". The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 10. Store registers other than those described in Figure 10 with program when the user needs them during interrupts or subroutine calls. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. b7 A b7 X b7 Y b7 S b15 PCH b7 b7 PCL b0 Accumulator b0 Index register X b0 Index register Y b0 Stack pointer b0 Program counter b0 Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag NVTBD I ZC Fig.9 740 Family CPU register structure Rev.4.01 Nov 14, 2003 page 11 of 136 3803/3804 Group On-going Routine Interrupt request (Note) Execute JSR M (S) Push return address on stack (S) M (S) (S) (PCH) (S) - 1 (PCL) (S)- 1 M (S) (S) M (S) (S) M (S) (S) (PCH) (S) - 1 (PCL) (S) - 1 (PS) (S) - 1 Push contents of processor status register on stack Push return address on stack Subroutine Execute RTS POP return address from stack (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S) Interrupt Service Routine Execute RTI (S) (PS) (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S) (S) + 1 M (S) I Flag is set from "0" to "1" Fetch the jump vector POP contents of processor status register from stack POP return address from stack Note: Condition for acceptance of an interrupt Interrupt enable flag is "1" Interrupt disable flag is "0" Fig. 10 Register push and pop at interrupt generation and subroutine call Table 4 Push and pop instructions of accumulator or processor status register Push instruction to stack Accumulator Processor status register PHA PHP Pop instruction from stack PLA PLP Rev.4.01 Nov 14, 2003 page 12 of 136 3803/3804 Group [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. *Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. *Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is "0", and cleared if the result is anything other than "0". *Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is "1". *Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is "0"; decimal arithmetic is executed when it is "1". Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. *Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always "0". When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to "1". *Bit 5: Index X mode flag (T) When the T flag is "0", arithmetic operations are performed between accumulator and memory. When the T flag is "1", direct arithmetic operations and direct data transfers are enabled between memory locations. *Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. *Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 5 Set and clear instructions of each bit of processor status register C flag Set instruction Clear instruction SEC CLC Z flag - - I flag SEI CLI D flag SED CLD B flag - - T flag SET CLT V flag - CLV N flag - - Rev.4.01 Nov 14, 2003 page 13 of 136 3803/3804 Group [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B16. b7 1 b0 CPU mode register (CPUM : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1: 1 0 : Not available 1 1: Stack page selection bit 0 : 0 page 1 : 1 page Fix this bit to "1". Port XC switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function Main clock (XIN-XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bits b7 b6 0 0 : = f(XIN)/2 (high-speed mode) 0 1 : = f(XIN)/8 (middle-speed mode) 1 0 : = f(XCIN)/2 (low-speed mode) 1 1 : Not available Fig.11 Structure of CPU mode register Rev.4.01 Nov 14, 2003 page 14 of 136 3803/3804 Group MISRG (1) Bit 0 of address 001016: Oscillation stabilizing time set after STP instruction released bit When the MCU stops the clock oscillation by the STP instruction and the STP instruction has been released by an external interrupt source, usually, the fixed values of Timer 1 and Prescaler 12 (Timer 1 = 0116, Prescaler 12 = FF16) are automatically reloaded in order for the oscillation to stabilize. The user can inhibit the automatic setting by setting "1" to bit 0 of MISRG (address 001016). However, by setting this bit to "1", the previous values, set just before the STP instruction was executed, will remain in Timer 1 and Prescaler 12. Therefore, you will need to set an appropriate value to each register, in accordance with the oscillation stabilizing time, before executing the STP instruction. Figure 12 shows the structure of MISRG. (2) Bits 1, 2, 3 of address 001016: Middle-speed Mode Automatic Switch Function In order to switch the clock mode of an MCU which has a subclock, the following procedure is necessary: set CPU mode register (003B16) --> start main clock oscillation --> wait for oscillation stabilization --> switch to middle-speed mode (or high-speed mode). However, the 3803/3804 group has the built-in function which automatically switches from low to middle-speed mode either by the SCL/SDA interrupt (only for the 3804 group) or by program. qMiddle-speed mode automatic switch by SCL/SDA Interrupt (only for 3804 group) The SCL/SDA interrupt source enables an automatic switch when the middle-speed mode automatic switch set bit (bit 1) of MISRG (address 001016) is set to "1". The conditions for an automatic switch execution depend on the settings of bits 5 and 6 of the I2C start/stop condition control register (address 001616). Bit 5 is the SCL/SDA interrupt pin polarity selection bit and bit 6 is the SCL/ SDA interrupt pin selection bit. The main clock oscillation stabilizing time can also be selected by middle-speed mode automatic switch wait time set bit (bit 2) of the MISRG. qMiddle-speed mode automatic switch by program The middle-speed mode can also be automatically switched by program while operating in low-speed mode. By setting the middle-speed automatic switch start bit (bit 3) of MISRG (address 001016) to "1" in the condition that the middle-speed mode automatic switch set bit is "1" while operating in low-speed mode, the MCU will automatically switch to middle-speed mode. In this case, the oscillation stabilizing time of the main clock can be selected by the middle-speed automatic switch wait time set bit (bit 2) of MISRG (address 001016). b7 b0 MISRG (MISRG : address 001016) Oscillation stabilizing time set after STP instruction released bit 0: Automatically set "0116" to Timer 1, "FF16" to Prescaler 12 1: Automatically set disabled Middle-speed mode automatic switch set bit 0: Not set automatically 1: Automatic switching enabled (Notes 1, 2) Middle-speed mode automatic switch wait time set bit 0: 4.5 to 5.5 machine cycles 1: 6.5 to 7.5 machine cycles Middle-speed mode automatic switch start bit (Depending on program) 0: Invalid 1: Automatic switch start (Note 2) Not used (return "0" when read) (Do not write "1" to this bit) Notes 1: During operation in low-speed mode, it is possible automatically to switch to middle-speed mode owing to SCL/SDA interrupt. This is valid only for the 3804 group. 2: When automatic switch to middle-speed mode from low-speed mode occurs, the values of CPU mode register (3B16) change. Fig.12 Structure of MISRG Rev.4.01 Nov 14, 2003 page 15 of 136 3803/3804 Group MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. Zero Page Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. Access to this area with only 2 bytes is possible in the special page addressing mode. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is a user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. RAM area RAM size (bytes) Address XXXX16 000016 SFR area 004016 010016 RAM Zero page 192 256 384 512 640 768 896 1024 1536 2048 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16 XXXX16 Not used 0FF016 0FFF16 SFR area Not used ROM area ROM size (bytes) Address YYYY16 Address ZZZZ16 YYYY16 Reserved ROM area (128 bytes) 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016 ZZZZ16 ROM FF0016 FFDC16 Interrupt vector area FFFE16 FFFF16 Special page Reserved ROM area Fig. 13 Memory map diagram Rev.4.01 Nov 14, 2003 page 16 of 136 3803/3804 Group 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Timer 12, X count source selection register (T12XCSS) Timer Y, Z count source selection register (TYZCSS) MISRG Reserved Reserved Reserved Reserved Reserved Reserved Reserved Transmit/Receive buffer register 1 (TB1/RB1) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART1 control register (UART1CON) Baud rate generator (BRG1) Serial I/O2 control register (SIO2CON) Watchdog timer control register (WDTCON) Serial I/O2 register (SIO2) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer XY mode register (TM) Prescaler X (PREX) Timer X (TX) Prescaler Y (PREY) Timer Y (TY) Timer Z low-order (TZL) Timer Z high-order (TZH) Timer Z mode register (TZM) PWM control register (PWMCON) PWM prescaler (PREPWM) PWM register (PWM) Baud rate generator 3 (BRG3) Transmit/Receive buffer register 3 (TB3/RB3) Serial I/O3 status register (SIO3STS) Serial I/O3 control register (SIO3CON) UART3 control register (UART3CON) AD/DA control register (ADCON) A-D conversion register 1 (AD1) D-A1 conversion register (DA1) D-A2 conversion register (DA2) A-D conversion register 2 (AD2) Interrupt source selection register (INTSEL) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) 0FF016 0FF116 0FF216 0FF316 0FF416 0FF516 0FF616 Port P0 pull-up control register (PULL0) Port P1 pull-up control register (PULL1) Port P2 pull-up control register (PULL2) Port P3 pull-up control register (PULL3) Port P4 pull-up control register (PULL4) Port P5 pull-up control register (PULL5) Port P6 pull-up control register (PULL6) Reserved area: Do not write any data to this addresses, because these areas are reserved. 0FFE16 0FFF16 Flash memory control register (FCON) Flash command register (FCMD) Fig. 14 Memory map of 3803 group's special function register (SFR) Rev.4.01 Nov 14, 2003 page 17 of 136 3803/3804 Group 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Timer 12, X count source selection register (T12XCSS) Timer Y, Z count source selection register (TYZCSS) MISRG I2C data shift register (S0) I2C special mode status register (S3) I2C status register (S1) I2C I2C control register (S1D) I2C clock control register (S2) START/STOP condition control register (S2D) I2C special mode control register (S3D) Transmit/Receive buffer register 1 (TB1/RB1) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART1 control register (UART1CON) Baud rate generator (BRG1) Serial I/O2 control register (SIO2CON) Watchdog timer control register (WDTCON) Serial I/O2 register (SIO2) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer XY mode register (TM) Prescaler X (PREX) Timer X (TX) Prescaler Y (PREY) Timer Y (TY) Timer Z low-order (TZL) Timer Z high-order (TZH) Timer Z mode register (TZM) PWM control register (PWMCON) PWM prescaler (PREPWM) PWM register (PWM) Baud rate generator 3 (BRG3) Transmit/Receive buffer register 3 (TB3/RB3) Serial I/O3 status register (SIO3STS) Serial I/O3 control register (SIO3CON) UART3 control register (UART3CON) AD/DA control register (ADCON) A-D conversion register 1 (AD1) D-A1 conversion register (DA1) D-A2 conversion register (DA2) A-D conversion register 2 (AD2) Interrupt source selection register (INTSEL) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) 0FF016 0FF116 0FF216 0FF316 0FF416 0FF516 0FF616 0FF716 0FF816 0FF916 0FFE16 0FFF16 Port P0 pull-up control register (PULL0) Port P1 pull-up control register (PULL1) Port P2 pull-up control register (PULL2) Port P3 pull-up control register (PULL3) Port P4 pull-up control register (PULL4) Port P5 pull-up control register (PULL5) Port P6 pull-up control register (PULL6) I2C slave address register 0 (S0D0) I2C slave address register 1 (S0D1) I2C slave address register 2 (S0D2) Flash memory control register (FCON) Flash command register (FCMD) Fig. 15 Memory map of 3804 group's special function register (SFR) Rev.4.01 Nov 14, 2003 page 18 of 136 3803/3804 Group I/O PORTS The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When "0" is written to the bit corresponding to a pin, that pin beTable 6 I/O port function of 3803 group Pin P00/AN8-P07/AN15 P10/INT41 P11/INT01 P12-P17 P20/LED0- P27/LED7 P30/DA1 P31/DA2 P32 P33 P34/RxD3 P35/TxD3 P36/SCLK3 P37/SRDY3 P40/INT40/XCIN P41/INT00/XCOUT P42/INT1 P43/INT2 P44/RxD1 P45/TxD1 P46/SCLK1 P47/SRDY1/CNTR2 Port P4 CMOS compatible input level CMOS 3-state output Port P2 Port P3 CMOS compatible input level CMOS 3-state output CMOS compatible input level N-channel open-drain output CMOS compatible input level CMOS 3-state output Name Port P0 Port P1 I/O Structure CMOS compatible input level CMOS 3-state output comes an input pin. When "1" is written to that bit, that pin becomes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Non-Port Function A-D converter input External interrupt input Related SFRs AD/DA control register Interrupt edge selection register Ref.No. (1) (2) (3) D-A converter output AD/DA control register (4) (5) Serial I/O3 function I/O Serial I/O3 control register UART3 control register Interrupt edge selection register CPU mode register Interrupt edge selection register Serial I/O1 control register UART1 control register Serial I/O1 control register Timer Z mode register Serial I/O2 control register (6) (7) (8) (9) (10) (11) (2) (6) (7) (8) (12) External interrupt input Sub-clock generating circuit External interrupt input Serial I/O1 function I/O Serial I/O1 function I/O Timer Z function I/O P50/SIN2 P51/SOUT2 P52/SCLK2 P53/SRDY2 P54/CNTR0 P55/CNTR1 P56/PWM P57/INT3 P60/AN0-P67/AN7 Port P5 CMOS compatible input level CMOS 3-state output Serial I/O2 function I/O (13) (14) (15) (16) Timer X, Y function I/O PWM output External interrupt input Port P6 CMOS compatible input level CMOS 3-state output A-D converter input Timer XY mode register PWM control register Interrupt edge selection register AD/DA control register (17) (18) (2) (1) Notes 1: Refer to the applicable sections how to use double-function ports as function I/O ports. 2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate. Rev.4.01 Nov 14, 2003 page 19 of 136 3803/3804 Group Table 7 I/O port function of 3804 group Name Pin P00/AN8-P07/AN15 Port P0 Port P1 P10/INT41 P11/INT01 P12-P17 P20/LED0- P27/LED7 P30/DA1 P31/DA2 P32/SDA P33/SCL Port P2 Port P3 CMOS compatible input level CMOS 3-state output CMOS compatible input level N-channel open-drain output CMOS/SMBUS input level (when selecting I2C-BUS interface function) P34/RxD3 P35/TxD3 P36/SCLK3 P37/SRDY3 P40/INT00/XCIN P41/INT40/XCOUT P42/INT1 P43/INT2 P44/RxD1 P45/TxD1 P46/SCLK1 P47/SRDY1/CNTR2 Serial I/O1 function I/O Timer Z function I/O P50/SIN2 P51/SOUT2 P52/SCLK2 P53/SRDY2 P54/CNTR0 P55/CNTR1 P56/PWM P57/INT3 P60/AN0-P67/AN7 Port P6 CMOS compatible input level CMOS 3-state output Notes 1: Refer to the applicable sections how to use double-function ports as function I/O ports. 2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate. PWM output External interrupt input A-D converter input PWM control register Interrupt edge selection register AD/DA control register (18) (2) (1) Timer X, Y function I/O Timer XY mode register Port P5 CMOS compatible input level CMOS 3-state output Serial I/O2 function I/O Serial I/O1 function I/O Port P4 CMOS compatible input level CMOS 3-state output External interrupt input Sub-clock generating circuit External interrupt input Interrupt edge selection register CPU mode register Interrupt edge selection register Serial I/O1 control register UART1 control register Serial I/O1 control register Timer Z mode register Serial I/O2 control register (2) (6) (7) (8) (12) CMOS compatible input level CMOS 3-state output Serial I/O3 function I/O Serial I/O3 control register UART3 control register (6) (7) (8) (9) (10) (11) D-A converter output I2C-BUS interface function I/O AD/DA control register I2C control register (4) (5) I/O Structure CMOS compatible input level CMOS 3-state output Non-Port Function A-D converter input External interrupt input Related SFRs AD/DA control register Interrupt edge selection register Ref.No. (1) (2) (3) (13) (14) (15) (16) (17) Rev.4.01 Nov 14, 2003 page 20 of 136 3803/3804 Group (1) Ports P0, P6 Pull-up control bit (2) Ports P10, P11, P42, P43, P57 Pull-up control bit Direction register Direction register Data bus Port latch Data bus Port latch A-D converter input Analog input pin selection bit Interrupt input (3) Ports P12 to P17, P2 Pull-up control bit Direction register (4) Ports P30, P31 Pull-up control bit Direction register Data bus Port latch Data bus Port latch D-A converter output DA1 output enable (P30) DA2 output enable (P31) (5) Ports P32, P33 (6) Ports P34, P44 Pull-up control bit Serial I/O enable bit Receive enable bit Direction register Direction register Data bus Port latch Data bus Port latch Serial I/O input (7) Ports P35, P45 Pull-up control bit Serial I/O enable bit Transmit enable bit Direction register P-channel output disable bit (8) Ports P36, P46 Serial I/O synchronous clock selection bit Pull-up control bit Serial I/O enable bit Serial I/O mode selection bit Serial I/O enable bit Direction register Data bus Port latch Data bus Port latch Serial I/O output Serial I/O clock output Serial I/O external clock input Fig. 16 Port block diagram of 3803 group (1) Rev.4.01 Nov 14, 2003 page 21 of 136 3803/3804 Group (9) Port P37 Pull-up control bit Serial I/O3 mode selection bit Serial I/O3 enable bit SRDY3 output enable bit Direction register (10) Port P40 Pull-up control bit Port XC switch bit Direction register Data bus Port latch Data bus Port latch INT40 interrupt input Serial I/O3 ready output Port P41 Port XC switch bit Oscillator (11) Port P41 Pull-up control bit (12) Port P47 Timer Z operating mode bits Bit 2 Bit 1 Bit 0 Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register Pull-up control bit Port XC switch bit Direction register Data bus Port latch Data bus Port latch INT00 interrupt input Sub-clock generating circuit input Timer output Serial I/O1 ready output CNTR2 interrupt input (13) Port P50 Pull-up control bit (14) Port P51 Pull-up control bit Serial I/O2 transmit completion signal Serial I/O2 port selection bit Direction register Direction register Data bus Port latch P-channel output disable bit Data bus Port latch Serial I/O2 input Serial I/O2 output Fig. 17 Port block diagram of 3803 group (2) Rev.4.01 Nov 14, 2003 page 22 of 136 3803/3804 Group (15) Port P52 Pull-up control bit Serial I/O2 synchronous clock selection bit (16) Port P53 Pull-up control bit Serial I/O2 port selection bit SRDY2 enable bit Direction register Direction register Data bus Data bus Port latch Port latch Serial I/O2 ready output Serial I/O2 clock output Serial I/O2 external clock input (17) Ports P54, P55 (18) Port P56 Pull-up control bit Pull-up control bit PWM output enable bit Direction register Direction register Data bus Port latch Data bus Port latch Pulse output mode Timer output PWM output CNTR interrupt input Fig. 18 Port block diagram of 3803 group (3) Rev.4.01 Nov 14, 2003 page 23 of 136 3803/3804 Group (1) Ports P0, P6 Pull-up control bit (2) Ports P10, P11, P42, P43, P57 Pull-up control bit Direction register Direction register Data bus Port latch Data bus Port latch A-D converter input Analog input pin selection bit Interrupt input (3) Ports P12 to P17, P2 Pull-up control bit Direction register (4) Ports P30, P31 Pull-up control bit Direction register Data bus Port latch Data bus Port latch D-A converter output DA1 output enable (P30) DA2 output enable (P31) (5) Ports P32, P33 I2C-BUS interface enable bit Direction register (6) Ports P34, P44 Pull-up control bit Serial I/O enable bit Receive enable bit Direction register Port latch Data bus Port latch Data bus SDA output SCL output SDA input SCL input Serial I/O input (7) Ports P35, P45 Pull-up control bit Serial I/O enable bit Transmit enable bit Direction register P-channel output disable bit (8) Ports P36, P46 Serial I/O synchronous clock selection bit Pull-up control bit Serial I/O enable bit Serial I/O mode selection bit Serial I/O enable bit Direction register Data bus Port latch Data bus Port latch Serial I/O output Serial I/O clock output Serial I/O external clock input Fig. 19 Port block diagram of 3804 group (1) Rev.4.01 Nov 14, 2003 page 24 of 136 3803/3804 Group (9) Port P37 Pull-up control bit Serial I/O3 mode selection bit Serial I/O3 enable bit SRDY3 output enable bit Direction register (10) Port P40 Pull-up control bit Port XC switch bit Direction register Data bus Port latch Data bus Port latch Serial I/O3 ready output INT40 interrupt input Oscillator Port P41 Port XC switch bit (11) Port P41 Pull-up control bit (12) Port P47 Timer Z operating mode bits Bit 2 Bit 1 Bit 0 Serial I/O1 mode selection bit SRDY1 output enable bit Serial I/O1 enable bit Direction register Pull-up control bit Port XC switch bit Direction register Data bus Port latch Data bus INT00 interrupt input Sub-clock generating circuit input Port latch Timer output Serial I/O1 ready output CNTR2 interrupt input (13) Port P50 Pull-up control bit (14) Port P51 Pull-up control bit Serial I/O2 transmit completion signal Serial I/O2 port selection bit Direction register Direction register Data bus Port latch P-channel output disable bit Data bus Port latch Serial I/O2 input Serial I/O2 output Fig. 20 Port block diagram of 3804 group (2) Rev.4.01 Nov 14, 2003 page 25 of 136 3803/3804 Group (15) Port P52 Pull-up control bit Serial I/O2 synchronous clock selection bit (16) Port P53 Pull-up control bit Serial I/O2 port selection bit SRDY2 output enable bit Direction register Direction register Data bus Data bus Port latch Port latch Serial I/O2 ready output Serial I/O2 clock output Serial I/O2 external clock input (17) Ports P54, P55 (18) Port P56 Pull-up control bit Pull-up control bit PWM output enable bit Direction register Direction register Data bus Port latch Data bus Port latch Pulse output mode Timer output CNTR interrupt input PWM output Fig. 21 Port block diagram of 3804 group (3) Rev.4.01 Nov 14, 2003 page 26 of 136 3803/3804 Group b7 b0 Port P0 pull-up control register (PULL0: address 0FF016) P00 pull-up control bit 0: No pull-up 1: Pull-up P01 pull-up control bit 0: No pull-up 1: Pull-up P02 pull-up control bit 0: No pull-up 1: Pull-up P03 pull-up control bit 0: No pull-up 1: Pull-up P04 pull-up control bit 0: No pull-up 1: Pull-up P05 pull-up control bit 0: No pull-up 1: Pull-up P06 pull-up control bit 0: No pull-up 1: Pull-up P07 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. b7 b0 Port P1 pull-up control register (PULL1: address 0FF116) P10 pull-up control bit 0: No pull-up 1: Pull-up P11 pull-up control bit 0: No pull-up 1: Pull-up P12 pull-up control bit 0: No pull-up 1: Pull-up P13 pull-up control bit 0: No pull-up 1: Pull-up P14 pull-up control bit 0: No pull-up 1: Pull-up P15 pull-up control bit 0: No pull-up 1: Pull-up P16 pull-up control bit 0: No pull-up 1: Pull-up P17 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. Fig. 22 Structure of port pull-up control register (1) Rev.4.01 Nov 14, 2003 page 27 of 136 3803/3804 Group b7 b0 Port P2 pull-up control register (PULL2: address 0FF216) P20 pull-up control bit 0: No pull-up 1: Pull-up P21 pull-up control bit 0: No pull-up 1: Pull-up P22 pull-up control bit 0: No pull-up 1: Pull-up P23 pull-up control bit 0: No pull-up 1: Pull-up P24 pull-up control bit 0: No pull-up 1: Pull-up P25 pull-up control bit 0: No pull-up 1: Pull-up P26 pull-up control bit 0: No pull-up 1: Pull-up P27 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. b7 b0 Port P3 pull-up control register (PULL3: address 0FF316) P30 pull-up control bit 0: No pull-up 1: Pull-up P31 pull-up control bit 0: No pull-up 1: Pull-up Not used (return "0" when read) P34 pull-up control bit 0: No pull-up 1: Pull-up P35 pull-up control bit 0: No pull-up 1: Pull-up P36 pull-up control bit 0: No pull-up 1: Pull-up P37 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. Fig. 23 Structure of port pull-up control register (2) Rev.4.01 Nov 14, 2003 page 28 of 136 3803/3804 Group b7 b0 Port P4 pull-up control register (PULL4: address 0FF416) P40 pull-up control bit 0: No pull-up 1: Pull-up P41 pull-up control bit 0: No pull-up 1: Pull-up P42 pull-up control bit 0: No pull-up 1: Pull-up P43 pull-up control bit 0: No pull-up 1: Pull-up P44 pull-up control bit 0: No pull-up 1: Pull-up P45 pull-up control bit 0: No pull-up 1: Pull-up P46 pull-up control bit 0: No pull-up 1: Pull-up P47 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. b7 b0 Port P5 pull-up control register (PULL5: address 0FF516) P50 pull-up control bit 0: No pull-up 1: Pull-up P51 pull-up control bit 0: No pull-up 1: Pull-up P52 pull-up control bit 0: No pull-up 1: Pull-up P53 pull-up control bit 0: No pull-up 1: Pull-up P54 pull-up control bit 0: No pull-up 1: Pull-up P55 pull-up control bit 0: No pull-up 1: Pull-up P56 pull-up control bit 0: No pull-up 1: Pull-up P57 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. Fig. 24 Structure of port pull-up control register (3) Rev.4.01 Nov 14, 2003 page 29 of 136 3803/3804 Group b7 b0 Port P6 pull-up control register (PULL6: address 0FF616) P60 pull-up control bit 0: No pull-up 1: Pull-up P61 pull-up control bit 0: No pull-up 1: Pull-up P62 pull-up control bit 0: No pull-up 1: Pull-up P63 pull-up control bit 0: No pull-up 1: Pull-up P64 pull-up control bit 0: No pull-up 1: Pull-up P65 pull-up control bit 0: No pull-up 1: Pull-up P66 pull-up control bit 0: No pull-up 1: Pull-up P67 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. Fig. 25 Structure of port pull-up control register (4) Rev.4.01 Nov 14, 2003 page 30 of 136 3803/3804 Group INTERRUPTS The 3803 group's interrupts are a type of vector and occur by 16 sources among 21 sources: eight external, twelve internal, and one software. The 3804 group's interrupts occur by 16 sources among 23 sources: nine external, thirteen internal, and one software. s Notes When setting the followings, the interrupt request bit may be set to "1". *When switching external interrupt active edge Related register: Interrupt edge selection register (address 3A16) Timer XY mode register (address 2316) Timer Z mode register (address 2A16) I2C start/stop condition control register (address 1616) (3804 group only) *When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register: Interrupt source selection register (address 3916) When not requiring for the interrupt occurrence synchronized with these setting, take the following sequence. Set the corresponding interrupt enable bit to "0" (disabled). Set the interrupt edge select bit or the interrupt source select bit. Set the corresponding interrupt request bit to "0" after 1 or more instructions have been executed. Set the corresponding interrupt enable bit to "1" (enabled). Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0". Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The reset and the BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the reset and the BRK instruction interrupt. When several interrupt requests occur at the same time, the interrupts are received according to priority. Interrupt Operation By acceptance of an interrupt, the following operations are automatically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter. Interrupt Source Selection Which of each combination of the following interrupt sources can be selected by the interrupt source selection register (address 003916). 1. INT0 or Timer Z 2. Serial I/O1 transmission or SCL, SDA (for 3804 group) 3. CNTR0 or SCL, SDA (for 3804 group) 4. CNTR1 or Serial I/O3 reception 5. Serial I/O2 or Timer Z 6. INT2 or I2C (for 3804 group) 7. INT4 or CNTR2 8. A-D converter or serial I/O3 transmission External Interrupt Pin Selection The occurrence sources of the external interrupt INT0 and INT4 can be selected from either input from INT00 and INT40 pin, or input from INT01 and INT41 pin by the INT0, INT4 interrupt switch bit of interrupt edge selection register (bit 6 of address 003A16). Rev.4.01 Nov 14, 2003 page 31 of 136 3803/3804 Group Table 8 Interrupt vector addresses and priority of 3803 group Interrupt Source Reset (Note 2) INT0 Timer Z INT1 Serial I/O1 reception Serial I/O1 transmission Timer X Timer Y Timer 1 Timer 2 CNTR0 CNTR1 Serial I/O3 reception Serial I/O2 Timer Z INT2 INT3 INT4 CNTR2 A-D converter Serial I/O3 transmission BRK instruction 16 FFDF16 FFDE16 13 14 15 FFE516 FFE316 FFE116 FFE416 FFE216 FFE016 12 FFE716 FFE616 3 4 5 FFF916 FFF716 FFF516 FFF816 FFF616 FFF416 Priority 1 2 Vector Addresses (Note 1) Low High FFFC16 FFFD16 FFFB16 FFFA16 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At timer Z underflow At detection of either rising or falling edge of INT1 input At completion of serial I/O1 data reception At completion of serial I/O1 transmission shift or when transmission buffer is empty At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At completion of serial I/O3 data reception At completion of serial I/O2 data transmission or reception At timer Z underflow At detection of either rising or falling edge of INT2 input At detection of either rising or falling edge of INT3 input At detection of either rising or falling edge of INT4 input At detection of either rising or falling edge of CNTR2 input At completion of A-D conversion At completion of serial I/O3 transmission shift or when transmission buffer is empty 17 FFDD16 FFDC16 At BRK instruction execution Valid when serial I/O3 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O3 is selected Valid when serial I/O2 is selected STP release timer underflow External interrupt (active edge selectable) Valid when serial I/O1 is selected Valid when serial I/O1 is selected Remarks Non-maskable External interrupt (active edge selectable) 6 7 8 9 10 11 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 Non-maskable software interrupt Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. Rev.4.01 Nov 14, 2003 page 32 of 136 3803/3804 Group Table 9 Interrupt vector addresses and priority of 3804 group Interrupt Source Reset (Note 2) INT0 Timer Z INT1 Serial I/O1 reception Serial I/O1 transmission SCL, SDA Timer X Timer Y Timer 1 Timer 2 CNTR0 SCL, SDA CNTR1 Serial I/O3 reception Serial I/O2 Timer Z INT2 I 2C INT3 INT4 CNTR2 A-D converter Serial I/O3 transmission BRK instruction 17 FFDD16 FFDC16 16 FFDF16 FFDE16 14 15 FFE316 FFE116 FFE216 FFE016 13 FFE516 FFE416 11 FFE916 FFE816 6 7 8 9 10 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFF216 FFF016 FFEE16 FFEC16 FFEA16 3 4 5 FFF916 FFF716 FFF516 FFF816 FFF616 FFF416 Priority 1 2 Vector Addresses (Note 1) Low High FFFC16 FFFD16 FFFB16 FFFA16 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At timer Z underflow At detection of either rising or falling edge of INT1 input At completion of serial I/O1 data reception At completion of serial I/O1 transmission shift or when transmission buffer is empty At detection of either rising or falling edge of SCL or SDA At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of SCL or SDA At detection of either rising or falling edge of CNTR1 input At completion of serial I/O3 data reception 12 FFE716 FFE616 At completion of serial I/O2 data transmission or reception At timer Z underflow At detection of either rising or falling edge of INT2 input At completion of data transfer At detection of either rising or falling edge of INT3 input At detection of either rising or falling edge of INT4 input At detection of either rising or falling edge of CNTR2 input At completion of A-D conversion At completion of serial I/O3 transmission shift or when transmission buffer is empty At BRK instruction execution Valid when serial I/O3 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O3 is selected Valid when serial I/O2 is selected STP release timer underflow External interrupt (active edge selectable) Valid when serial I/O1 is selected Valid when serial I/O1 is selected Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Non-maskable software interrupt Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. Rev.4.01 Nov 14, 2003 page 33 of 136 3803/3804 Group Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Interrupt request Fig. 26 Interrupt control Rev.4.01 Nov 14, 2003 page 34 of 136 3803/3804 Group b7 b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 active edge selection bit INT1 active edge selection bit Not used (returns "0" when read) INT2 active edge selection bit INT3 active edge selection bit INT4 active edge selection bit INT0, INT4 interrupt switch bit 0 : INT00, INT40 interrupt 1 : INT01, INT41 interrupt Not used (returns "0" when read) 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active b7 b0 Interrupt request register 1 (IREQ1 : address 003C16) INT0/Timer Z interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit b7 b0 Interrupt request register 2 (IREQ2 : address 003D16) CNTR0 interrupt request bit CNTR1/Serial I/O3 receive interrupt request bit Serial I/O2/Timer Z interrupt request bit INT2 interrupt request bit INT3 interrupt request bit INT4/CNTR2 interrupt request bit AD converter/Serial I/O3 transmit interrupt request bit Not used (returns "0" when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 1 (ICON1 : address 003E16) INT0/Timer Z interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit b7 b0 Interrupt control register 2 (ICON2 : address 003F16) CNTR0 interrupt enable bit CNTR1/Serial I/O3 receive interrupt enable bit Serial I/O2/Timer Z interrupt enable bit INT2 interrupt enable bit INT3 interrupt enable bit INT4/CNTR2 interrupt enable bit AD converter/Serial I/O3 transmit interrupt enable bit Not used (returns "0" when read) 0 : Interrupts disabled 1 : Interrupts enabled b7 b0 Interrupt source selection register (INTSEL: address 003916) INT0/Timer Z interrupt source selection bit 0 : INT0 interrupt 1 : Timer Z interrupt Serial I/O2/Timer Z interrupt source selection bit 0 : Serial I/O2 interrupt 1 : Timer Z interrupt Not used (Do not write "1" to these bits.) INT4/CNTR2 interrupt source selection bit 0 : INT4 interrupt 1 : CNTR2 interrupt Not used (Do not write "1" to this bit.) CNTR1/Serial I/O3 receive interrupt source selection bit 0 : CNTR1 interrupt 1 : Serial I/O3 receive interrupt AD converter/Serial I/O3 transmit interrupt source selection bit 0 : A-D converter interrupt 1 : Serial I/O3 transmit interrupt (Do not write "1" to these bits simultaneously.) Fig. 27 Structure of interrupt-related registers of 3803 group Rev.4.01 Nov 14, 2003 page 35 of 136 3803/3804 Group b7 b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 active edge selection bit INT1 active edge selection bit Not used (returns "0" when read) INT2 active edge selection bit INT3 active edge selection bit INT4 active edge selection bit INT0, INT4 interrupt switch bit 0 : INT00, INT40 interrupt 1 : INT01, INT41 interrupt Not used (returns "0" when read) 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active b7 b0 Interrupt request register 1 (IREQ1 : address 003C16) INT0/Timer Z interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit/SCL, SDA interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit b7 b0 Interrupt request register 2 (IREQ2 : address 003D16) CNTR0/SCL, SDA interrupt request bit CNTR1/Serial I/O3 receive interrupt request bit Serial I/O2/Timer Z interrupt request bit INT2/I2C interrupt request bit INT3 interrupt request bit INT4/CNTR2 interrupt request bit AD converter/Serial I/O3 transmit interrupt request bit Not used (returns "0" when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 2 (ICON2 : address 003F16) CNTR0/SCL, SDA interrupt enable bit CNTR1/Serial I/O3 receive interrupt enable bit Serial I/O2/Timer Z interrupt enable bit INT2/I2C interrupt enable bit INT3 interrupt enable bit INT4/CNTR2 interrupt enable bit AD converter/Serial I/O3 transmit interrupt enable bit Not used (returns "0" when read) 0 : Interrupts disabled 1 : Interrupts enabled b7 b0 Interrupt control register 1 (ICON1 : address 003E16) INT0/Timer Z interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit/SCL, SDA interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit b7 b0 Interrupt source selection register (INTSEL: address 003916) INT0/Timer Z interrupt source selection bit 0 : INT0 interrupt 1 : Timer Z interrupt (Do not write "1" to these bits simultaneously.) Serial I/O2/Timer Z interrupt source selection bit 0 : Serial I/O2 interrupt 1 : Timer Z interrupt Serial I/O1 transmit/SCL, SDA interrupt source selection bit 0 : Serial I/O1 transmit interrupt 1 : SCL, SDA interrupt (Do not write "1" to these bits simultaneously.) CNTR0/SCL, SDA interrupt source selection bit 0 : CNTR0 interrupt 1 : SCL, SDA interrupt INT4/CNTR2 interrupt source selection bit 0 : INT4 interrupt 1 : CNTR2 interrupt INT2/I2C interrupt source selection bit 0 : INT2 interrupt 1 : I2C interrupt CNTR1/Serial I/O3 receive interrupt source selection bit 0 : CNTR1 interrupt 1 : Serial I/O3 receive interrupt AD converter/Serial I/O3 transmit interrupt source selection bit 0 : A-D converter interrupt 1 : Serial I/O3 transmit interrupt Fig. 28 Structure of interrupt-related registers of 3804 group Rev.4.01 Nov 14, 2003 page 36 of 136 3803/3804 Group TIMERS q8-bit Timers The 3803/3804 group has four 8-bit timers: timer 1, timer 2, timer X, and timer Y. The timer 1 and timer 2 use one prescaler in common, and the timer X and timer Y use each prescaler. Those are 8-bit prescalers. Each of the timers and prescalers has a timer latch or a prescaler latch. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. All timers are down-counters. When the timer reaches "0016", an underflow occurs at the next count pulse and the contents of the corresponding timer latch are reloaded into the timer and the count is continued. When the timer underflows, the interrupt request bit corresponding to that timer is set to "1". qTimer divider The divider count source is switched by the main clock division ratio selection bits of CPU mode register (bits 7 and 6 at address 003B16). When these bits are "00" (high-speed mode) or "01" (middle-speed mode), XIN is selected. When these bits are"10" (low-speed mode), XCIN is selected. qPrescaler 12 The prescaler 12 counts the output of the timer divider. The count source is selected by the timer 12, X count source selection register among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024 of f(XIN) or f(XCIN). Timer X and Timer Y The timer X and timer Y can each select one of four operating modes by setting the timer XY mode register (address 002316). (1) Timer mode qMode selection This mode can be selected by setting "00" to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). qExplanation of operation The timer count operation is started by setting "0" to the timer X count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the timer XY mode register (address 002316). When the timer reaches "0016", an underflow occurs at the next count pulse and the contents of timer latch are reloaded into the timer and the count is continued. (2) Pulse output mode qMode selection This mode can be selected by setting "01" to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). qExplanation of operation The operation is the same as the timer mode's. Moreover the pulse which is inverted each time the timer underflows is output from CNTR0/CNTR1 pin. When the CNTR0 active edge switch bit (bit 2) and the CNTR1 active edge switch bit (bit 6) of the timer XY mode register (address 002316) is "0", the output starts with "H" level. When it is "1", the output starts with "L" level. When the value of the CNTR0/CNTR1 active edge switch bit is changed during pulse output, the output level of the CNTR0/ CNTR1 pin is inverted. sPrecautions Set the double-function port of CNTR0/CNTR1 pin and port P54/ P55 to output in this mode. Timer 1 and Timer 2 The timer 1 and timer 2 counts the output of prescaler 12 and periodically set the interrupt request bit. qPrescaler X and prescaler Y The prescaler X and prescaler Y count the output of the timer divider or f(XCIN). The count source is selected by the timer 12, X count source selection register (address 000E16) and the timer Y, Z count source selection register (address 000F16) among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, and 1/1024 of f(XIN) or f(XCIN); and f(XCIN). Rev.4.01 Nov 14, 2003 page 37 of 136 3803/3804 Group (3) Event counter mode qMode selection This mode can be selected by setting "10" to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). qExplanation of operation The operation is the same as the timer mode's except that the timer counts signals input from the CNTR0 or CNTR1 pin. The valid edge for the count operation depends on the CNTR0 active edge switch bit (bit 2) or the CNTR1 active edge switch bit (bit 6) of the timer XY mode register (address 002316). When it is "0", the rising edge is valid. When it is "1", the falling edge is valid. sPrecautions Set the double-function port of CNTR0/CNTR1 pin and port P54/ P55 to input in this mode. (4) Pulse width measurement mode qMode selection This mode can be selected by setting "11" to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). qExplanation of operation When the CNTR0 active edge switch bit (bit 2) or the CNTR1 active edge switch bit (bit 6) of the timer XY mode register (address 002316) is "1", the timer counts during the term of one falling edge of CNTR0/CNTR1 pin input until the next rising edge of input ("L" term). When it is "0", the timer counts during the term of one rising edge input until the next falling edge input ("H" term). sPrecautions Set the double-function port of CNTR0/CNTR1 pin and port P54/ P55 to input in this mode. The count operation can be stopped by setting "1" to the timer X count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the timer XY mode register (address 002316). The interrupt request bit is set to "1" each time the timer underflows. *Precautions when switching count source When switching the count source by the timer 12, X and Y count source selection bits, the value of timer count is altered in inconsiderable amount owing to generating of thin pulses on the count input signals. Therefore, select the timer count source before setting the value to the prescaler and the timer. Rev.4.01 Nov 14, 2003 page 38 of 136 3803/3804 Group XIN "00" "01" (1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024) Divider Count source selection bit Data bus XCIN Clock for timer 12 Clock for timer Y Main clock division ratio selection bits Clock for timer X "10" Prescaler X latch (8) f(XCIN) Pulse width measurement mode Timer mode Pulse output mode Prescaler X (8) CNTR0 active edge switch bit "0" "1" CNTR0 active edge switch bit "1" Q Q Event counter mode Timer X count stop bit Timer X latch (8) Timer X (8) To timer X interrupt request bit P54/CNTR0 To CNTR0 interrupt request bit Toggle flip-flop T R Timer X latch write pulse Pulse output mode Port P54 direction register Port P54 latch "0" Pulse output mode Data bus Count source selection bit Clock for timer Y f(XCIN) Pulse width measurement mode Prescaler Y latch (8) Timer mode Pulse output mode Prescaler Y (8) Timer Y latch (8) Timer Y (8) P55/CNTR1 CNTR1 active edge switch bit "0" "1" To timer Y interrupt request bit Event counter mode Timer Y count stop bit To CNTR1 interrupt request bit CNTR1 active edge switch bit "1" Q Toggle flip-flop T Q R Timer Y latch write pulse Pulse output mode Port P55 direction register Port P55 latch "0" Pulse output mode Data bus Prescaler 12 latch (8) Timer 1 latch (8) Timer 2 latch (8) Clock for timer 12 Prescaler 12 (8) Timer 1 (8) Timer 2 (8) To timer 2 interrupt request bit To timer 1 interrupt request bit Fig. 29 Block diagram of timer X, timer Y, timer 1, and timer 2 Rev.4.01 Nov 14, 2003 page 39 of 136 3803/3804 Group b7 b0 Timer XY mode register (TM : address 002316) Timer X operating mode bits b1 b0 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR0 active edge switch bit 0 : Interrupt at falling edge Count at rising edge in event counter mode 1 : Interrupt at rising edge Count at falling edge in event counter mode Timer X count stop bit 0 : Count start 1 : Count stop Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR1 active edge switch bit 0 : Interrupt at falling edge Count at rising edge in event counter mode 1 : Interrupt at rising edge Count at falling edge in event counter mode Timer Y count stop bit 0 : Count start 1 : Count stop Fig. 30 Structure of timer XY mode register Rev.4.01 Nov 14, 2003 page 40 of 136 3803/3804 Group b7 b0 Timer 12, X count source selection register (T12XCSS : address 000E16) Timer 12 count source selection bits b3b2b1b0 1010 : 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 1011 : 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 1100 : 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 1101 : 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 1110 : 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 1111 : 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 Timer X count source selection bits b7b6b5b4 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 1 0 1 0 : f(XCIN) b7 b0 Not used 1011 : 1100 : 1101 : 1110 : 1111 : Not used Timer Y, Z count source selection register (TYZCSS : address 000F16) Timer Y count source selection bits b3b2b1b0 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 1011 : 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 1100 : 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 1101 : 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 1110 : 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 1111 : 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 1 0 1 0 : f(XCIN) Timer Z count source selection bits b7b6b5b4 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 1 0 1 0 : f(XCIN) Not used 1011 : 1100 : 1101 : 1110 : 1111 : Not used Fig. 31 Structure of timer 12, X and timer Y, Z count source selection registers Rev.4.01 Nov 14, 2003 page 41 of 136 3803/3804 Group q16-bit Timers The timer Z is a 16-bit timer. When the timer reaches "000016", an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When the timer underflows, the interrupt request bit corresponding to the timer Z is set to "1". When reading/writing to the timer Z, perform reading/writing to both the high-order byte and the low-order byte. When reading the timer Z, read from the high-order byte first, followed by the low-order byte. Do not perform the writing to the timer Z between read operation of the high-order byte and read operation of the low-order byte. When writing to the timer Z, write to the low-order byte first, followed by the high-order byte. Do not perform the reading to the timer Z between write operation of the low-order byte and write operation of the high-order byte. The timer Z can select the count source by the timer Z count source selection bits of timer Y, Z count source selection register (bits 7 to 4 at address 000F16). Timer Z can select one of seven operating modes by setting the timer Z mode register (address 002A16). (2) Event counter mode qMode selection This mode can be selected by setting "000" to the timer Z operating mode bits (bits 2 to 0) and setting "1" to the timer/event counter mode switch bit (bit 7) of the timer Z mode register (address 002A16). The valid edge for the count operation depends on the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16). When it is "0", the rising edge is valid. When it is "1", the falling edge is valid. qInterrupt The interrupt at an underflow is the same as the timer mode's. qExplanation of operation The operation is the same as the timer mode's. Set the double-function port of CNTR2 pin and port P47 to input in this mode. Figure 34 shows the timing chart of the timer/event counter mode. (3) Pulse output mode qMode selection This mode can be selected by setting "001" to the timer Z operating mode bits (bits 2 to 0) and setting "0" to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). qCount source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/ 128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/ 512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. qInterrupt The interrupt at an underflow is the same as the timer mode's. qExplanation of operation The operation is the same as the timer mode's. Moreover the pulse which is inverted each time the timer underflows is output from CNTR2 pin. When the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16) is "0", the output starts with "H" level. When it is "1", the output starts with "L" level. sPrecautions Set the double-function port of CNTR2 pin and port P47 to output in this mode. [During timer operation stop] The output from CNTR2 pin is initialized to the level depending on CNTR2 active edge switch bit by writing to the timer. [During timer operation enabled] When the value of the CNTR2 active edge switch bit is changed, the output level of CNTR2 pin is inverted. Figure 35 shows the timing chart of the pulse output mode. (1) Timer mode qMode selection This mode can be selected by setting "000" to the timer Z operating mode bits (bits 2 to 0) and setting "0" to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). qCount source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/ 128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/ 512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. qInterrupt When an underflow occurs, the INT0/timer Z interrupt request bit (bit 0) of the interrupt request register 1 (address 003C16) is set to "1". qExplanation of operation During timer stop, usually write data to a latch and a timer at the same time to set the timer value. The timer count operation is started by setting "0" to the timer Z count stop bit (bit 6) of the timer Z mode register (address 002A16). When the timer reaches "000016", an underflow occurs at the next count pulse and the contents of timer latch are reloaded into the timer and the count is continued. When writing data to the timer during operation, the data is written only into the latch. Then the new latch value is reloaded into the timer at the next underflow. Rev.4.01 Nov 14, 2003 page 42 of 136 3803/3804 Group (4) Pulse period measurement mode qMode selection This mode can be selected by setting "010" to the timer Z operating mode bits (bits 2 to 0) and setting "0" to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). qCount source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. qInterrupt The interrupt at an underflow is the same as the timer mode's. When the pulse period measurement is completed, the INT4/ CNTR2 interrupt request bit (bit 5) of the interrupt request register 2 (address 003D16) is set to "1". qExplanation of operation The cycle of the pulse which is input from the CNTR2 pin is measured. When the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16) is "0", the timer counts during the term from one falling edge of CNTR2 pin input to the next falling edge. When it is "1", the timer counts during the term from one rising edge input to the next rising edge input. When the valid edge of measurement completion/start is detected, the 1's complement of the timer value is written to the timer latch and "FFFF16" is set to the timer. Furthermore when the timer underflows, the timer Z interrupt request occurs and "FFFF16" is set to the timer. When reading the timer Z, the value of the timer latch (measured value) is read. The measured value is retained until the next measurement completion. sPrecautions Set the double-function port of CNTR2 pin and port P47 to input in this mode. A read-out of timer value is impossible in this mode. The timer can be written to only during timer stop (no measurement of pulse period). Since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operation during measurement. "FFFF16" is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse period measurement depends on the timer value just before measurement start. Figure 36 shows the timing chart of the pulse period measurement mode. (5) Pulse width measurement mode qMode selection This mode can be selected by setting "011" to the timer Z operating mode bits (bits 2 to 0) and setting "0" to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). qCount source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. qInterrupt The interrupt at an underflow is the same as the timer mode's. When the pulse widths measurement is completed, the INT4/ CNTR2 interrupt request bit (bit 5) of the interrupt request register 2 (address 003D16) is set to "1". qExplanation of operation The pulse width which is input from the CNTR2 pin is measured. When the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16) is "0", the timer counts during the term from one rising edge input to the next falling edge input ("H" term). When it is "1", the timer counts during the term from one falling edge of CNTR2 pin input to the next rising edge of input ("L" term). When the valid edge of measurement completion is detected, the 1's complement of the timer value is written to the timer latch and "FFFF16" is set to the timer. When the timer Z underflows, the timer Z interrupt occurs and "FFFF16" is set to the timer Z. When reading the timer Z, the value of the timer latch (measured value) is read. The measured value is retained until the next measurement completion. sPrecautions Set the double-function port of CNTR2 pin and port P47 to input in this mode. A read-out of timer value is impossible in this mode. The timer can be written to only during timer stop (no measurement of pulse widths). Since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operation during measurement. "FFFF16" is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse width measurement depends on the timer value just before measurement start. Figure 37 shows the timing chart of the pulse width measurement mode. Rev.4.01 Nov 14, 2003 page 43 of 136 3803/3804 Group (6) Programmable waveform generating mode qMode selection This mode can be selected by setting "100" to the timer Z operating mode bits (bits 2 to 0) and setting "0" to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). qCount source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/ 512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. qInterrupt The interrupt at an underflow is the same as the timer mode's. qExplanation of operation The operation is the same as the timer mode's. Moreover the timer outputs the data set in the output level latch (bit 4) of the timer Z mode register (address 002A16) from the CNTR2 pin each time the timer underflows. Changing the value of the output level latch and the timer latch after an underflow makes it possible to output an optional waveform from the CNTR2 pin. sPrecautions Set the double-function port of CNTR2 pin and port P47 to output in this mode. Figure 38 shows the timing chart of the programmable waveform generating mode. though "H" is output from the CNTR2 pin, "H" output state continues because an underflow does not occur. *"L" one-shot pulse; Bit 5 of timer Z mode register = "1" The output level of the CNTR2 pin is initialized to "H" at mode selection. When trigger generation (input signal to INT1 pin) is detected, "L" is output from the CNTR2 pin. When an underflow occurs, "H" is output. The "L" one-shot pulse width is set by the setting value to the timer Z low-order and high-order. When trigger generating is detected during timer count stop, although "L" is output from the CNTR2 pin, "L" output state continues because an underflow does not occur. sPrecautions Set the double-function port of CNTR2 pin and port P47 to output, and of INT1 pin and port P42 to input in this mode. This mode cannot be used in low-speed mode. If the value of the CNTR2 active edge switch bit is changed during one-shot generating enabled or generating one-shot pulse, then the output level from CNTR2 pin changes. Figure 39 shows the timing chart of the programmable one-shot generating mode. sNotes regarding all modes qTimer Z write control Which write control can be selected by the timer Z write control bit (bit 3) of the timer Z mode register (address 002A16), writing data to both the latch and the timer at the same time or writing data only to the latch. When the operation "writing data only to the latch" is selected, the value is set to the timer latch by writing data to the address of timer Z and the timer is updated at next underflow. After reset release, the operation "writing data to both the latch and the timer at the same time" is selected, and the value is set to both the latch and the timer at the same time by writing data to the address of timer Z. In the case of writing data only to the latch, if writing data to the latch and an underflow are performed almost at the same time, the timer value may become undefined. qTimer Z read control A read-out of timer value is impossible in pulse period measurement mode and pulse width measurement mode. In the other modes, a read-out of timer value is possible regardless of count operating or stopped. However, a read-out of timer latch value is impossible. qSwitch of interrupt active edge of CNTR2 and INT1 Each interrupt active edge depends on setting of the CNTR2 active edge switch bit and the INT1 active edge selection bit. qSwitch of count source When switching the count source by the timer Z count source selection bits, the value of timer count is altered in inconsiderable amount owing to generating of thin pulses on the count input signals. Therefore, select the timer count source before setting the value to the prescaler and the timer. (7) Programmable one-shot generating mode qMode selection This mode can be selected by setting "101" to the timer Z operating mode bits (bits 2 to 0) and setting "0" to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). qCount source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/ 128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. qInterrupt The interrupt at an underflow is the same as the timer mode's. The trigger to generate one-shot pulse can be selected by the INT1 active edge selection bit (bit 1) of the interrupt edge selection register (address 003A16). When it is "0", the falling edge active is selected; when it is "1", the rising edge active is selected. When the valid edge of the INT1 pin is detected, the INT1 interrupt request bit (bit 1) of the interrupt request register 1 (address 003C16) is set to "1". qExplanation of operation *"H" one-shot pulse; Bit 5 of timer Z mode register = "0" The output level of the CNTR2 pin is initialized to "L" at mode selection. When trigger generation (input signal to INT1 pin) is detected, "H" is output from the CNTR2 pin. When an underflow occurs, "L" is output. The "H" one-shot pulse width is set by the setting value to the timer Z register low-order and high-order. When trigger generating is detected during timer count stop, al- Rev.4.01 Nov 14, 2003 page 44 of 136 3803/3804 Group CNTR2 active edge Data bus switch bit Programmable one-shot P42/INT1 Programmable one-shot generating mode "1" Programmable one-shot generating circuit "0" generating mode Programmable waveform generating mode Output level latch D T Q To INT1 interrupt request bit Pulse output mode CNTR2 active edge switch bit S Q Q "1" "001" "100" "101" "0" T Pulse output mode Timer Z operating mode bits Port P47 direction register Timer Z low-order latch Port P47 latch Timer Z low-order Timer Z high-order latch Timer Z high-order To timer Z interrupt request bit Pulse period measurement mode Pulse width measurement mode Edge detection circuit To CNTR2 interrupt request bit "1" "1" CNTR2 active edge switch bit "0" Clock for timer Z P47/CNTR2 f(XCIN) "0" Timer/Event counter mode switch bit Timer Z count stop bit XIN XCIN Count source Divider selection bit (1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024) Fig. 32 Block diagram of timer Z Rev.4.01 Nov 14, 2003 page 45 of 136 3803/3804 Group b7 b0 Timer Z mode register (TZM : address 002A16) Timer Z operating mode bits b2b1b0 0 0 0 : Timer/Event counter mode 0 0 1 : Pulse output mode 0 1 0 : Pulse period measurement mode 0 1 1 : Pulse width measurement mode 1 0 0 : Programmable waveform generating mode 1 0 1 : Programmable one-shot generating mode 1 1 0 : Not available 1 1 1 : Not available Timer Z write control bit 0 : Writing data to both latch and timer simultaneously 1 : Writing data only to latch Output level latch 0 : "L" output 1 : "H" output CNTR2 active edge switch bit 0 : *Event counter mode: Count at rising edge *Pulse output mode: Start outputting "H" *Pulse period measurement mode: Measurement between two falling edges *Pulse width measurement mode: Measurement of "H" term *Programmable one-shot generating mode: After start outputting "L", "H" one-shot pulse generated *Interrupt at falling edge 1 : *Event counter mode: Count at falling edge *Pulse output mode: Start outputting "L" *Pulse period measurement mode: Measurement between two rising edges *Pulse width measurement mode: Measurement of "L" term *Programmable one-shot generating mode: After start outputting "H", "L" one-shot pulse generated *Interrupt at rising edge Timer Z count stop bit 0 : Count start 1 : Count stop Timer/Event counter mode switch bit (Note) 0 : Timer mode 1 : Event counter mode Note: When selecting the modes except the timer/event counter mode, set "0" to this bit. Fig. 33 Structure of timer Z mode register Rev.4.01 Nov 14, 2003 page 46 of 136 3803/3804 Group FFFF16 TL 000016 TR TR TR TL : Value set to timer latch TR : Timer interrupt request Fig. 34 Timing chart of timer/event counter mode FFFF16 TL 000016 TR TR TR TR Waveform output from CNTR2 pin CNTR2 CNTR2 TL : Value set to timer latch TR : Timer interrupt request CNTR2 : CNTR2 interrupt request (CNTR2 active edge switch bit = "0"; Falling edge active) Fig. 35 Timing chart of pulse output mode Rev.4.01 Nov 14, 2003 page 47 of 136 3803/3804 Group 000016 T3 T2 T1 FFFF16 TR FFFF16 + T1 Signal input from CNTR2 pin CNTR2 CNTR2 CNTR2 of rising edge active TR : Timer interrupt request CNTR2 : CNTR2 interrupt request Fig. 36 Timing chart of pulse period measurement mode (Measuring term between two rising edges) TR T2 T3 FFFF16 CNTR2 CNTR2 000016 T3 T2 T1 FFFF16 TR Signal input from CNTR2 pin FFFF16 + T2 T3 T1 CNTR2 CNTR2 CNTR2 CNTR2 interrupt of rising edge active; Measurement of "L" width TR : Timer interrupt request CNTR2 : CNTR2 interrupt request Fig. 37 Timing chart of pulse width measurement mode (Measuring "L" term) Rev.4.01 Nov 14, 2003 page 48 of 136 3803/3804 Group FFFF16 T3 L T2 T1 000016 Signal output from CNTR2 pin L TR T1 T3 T2 TR TR TR CNTR2 CNTR2 L : Timer initial value TR : Timer interrupt request CNTR2 : CNTR2 interrupt request (CNTR2 active edge switch bit = "0"; Falling edge active) Fig. 38 Timing chart of programmable waveform generating mode FFFF16 L Signal input from INT1 pin Signal output from CNTR2 pin TR TR TR L CNTR2 L CNTR2 L L : One-shot pulse width TR : Timer interrupt request CNTR2 : CNTR2 interrupt request (CNTR2 active edge switch bit = "0"; Falling edge active) Fig. 39 Timing chart of programmable one-shot generating mode ("H" one-shot pulse generating) Rev.4.01 Nov 14, 2003 page 49 of 136 3803/3804 Group SERIAL I/O Serial I/O1 Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O1 mode can be selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register (bit 6 of address 001A16) to "1". For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. Data bus Serial I/O1 control register Address 001A16 Address 001816 Receive buffer register 1 Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit P44/RXD1 Receive shift register 1 Shift clock P46/SCLK1 BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 P47/SRDY1 F/F Falling-edge detector Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 1 1/4 Address 001C16 Clock control circuit Shift clock Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 P45/TXD1 Transmit shift register 1 Transmit buffer register 1 Address 001816 Data bus Fig. 40 Block diagram of clock synchronous serial I/O1 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD1 Serial input RxD1 D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Receive enable signal SRDY1 Write pulse to receive/transmit buffer register (address 001816) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection TBE = 1 TSC = 0 Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" . Fig. 41 Operation of clock synchronous serial I/O1 Rev.4.01 Nov 14, 2003 page 50 of 136 3803/3804 Group (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit of the serial I/O1 control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in a memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Data bus Address 001816 OE Character length selection bit ST detector 7 bits Receive shift register 1 8 bits PE FE SP detector Clock control circuit Serial I/O1 synchronous clock selection bit P46/SCLK1 BRG count source selection bit Frequency division ratio 1/(n+1) f(XIN) Baud rate generator (f(XCIN) in low-speed mode) Address 001C16 1/4 ST/SP/PA generator 1/16 P45/TXD1 Character length selection bit Transmit buffer register 1 Transmit shift register 1 Receive buffer register 1 Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 UART control register Address 001B16 P44/RXD1 Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Address 001816 Data bus Fig. 42 Block diagram of UART serial I/O1 Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 TBE=0 TBE=1 TSC=1] Serial output TXD1 ST D0 D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) SP ST D0 D1 ] SP Generated at 2nd bit in 2-stop-bit mode Receive buffer read signal RBF=0 RBF=1 RBF=1 Serial input RXD1 ST D0 D1 SP ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes "1," can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1." 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0. Fig. 43 Operation of UART serial I/O1 Rev.4.01 Nov 14, 2003 page 51 of 136 3803/3804 Group [Serial I/O1 Control Register (SIO1CON)] 001A16 The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART1 Control Register (UART1CON)] 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer, and one bit (bit 4) which is always valid and sets the output structure of the P45/TXD1 pin. [Serial I/O1 Status Register (SIO1STS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O1 status register are initialized to "0" at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to "1", the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1". [Transmit Buffer Register 1/Receive Buffer Register 1 (TB1/RB1)] 001816 The transmit buffer register 1 and the receive buffer register 1 are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0". [Baud Rate Generator 1 (BRG1)] 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. Rev.4.01 Nov 14, 2003 page 52 of 136 3803/3804 Group b7 b0 Serial I/O1 status register (SIO1STS : address 001916) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read) b7 b0 Serial I/O1 control register (SIO1CON : address 001A16) BRG count source selection bit (CSS) 0: f(XIN) (f(XCIN) in low-speed mode) 1: f(XIN)/4 (f(XCIN)/4 in low-speed mode) Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P47 pin operates as normal I/O pin 1: P47 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P44 to P47 operate as normal I/O pins) 1: Serial I/O1 enabled (pins P44 to P47 operate as serial I/O pins) b7 b0 UART1 control register (UARTCON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P45/TXD1 P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return "1" when read) Fig. 44 Structure of serial I/O1 control registers Rev.4.01 Nov 14, 2003 page 53 of 136 3803/3804 Group s Notes concerning serial I/O1 1. Notes when selecting clock synchronous serial I/O 1.1 Stop of transmission operation q Note Clear the serial I/O1 enable bit and the transmit enable bit to "0" (serial I/O and transmit disabled). q Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to "0" (serial I/O disabled), the internal transmission is running (in this case, since pins TxD1, RxD1, SCLK1, and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to "1" at this time, the data during internally shifting is output to the TxD1 pin and an operation failure occurs. 1.2 Stop of receive operation q Note Clear the receive enable bit to "0" (receive disabled), or clear the serial I/O1 enable bit to "0" (serial I/O disabled). 1.3 Stop of transmit/receive operation q Note Clear both the transmit enable bit and receive enable bit to "0" (transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data transmission and reception cannot be stopped.) q Reason In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to "0" (transmit disabled). Also, the transmission circuit is not initialized by clearing the serial I/O1 enable bit to "0" (serial I/O disabled) (refer to 1.1). 2. Notes when selecting clock asynchronous serial I/O 2.1 Stop of transmission operation q Note Clear the transmit enable bit to "0" (transmit disabled). The transmission operation does not stop by clearing the serial I/O1 enable bit to "0". q Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to "0" (serial I/O disabled), the internal transmission is running (in this case, since pins TxD1, RxD1, SCLK1, and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to "1" at this time, the data during internally shifting is output to the TxD1 pin and an operation failure occurs. 2.2 Stop of receive operation q Note Clear the receive enable bit to "0" (receive disabled). 2.3 Stop of transmit/receive operation q Note 1 (only transmission operation is stopped) Clear the transmit enable bit to "0" (transmit disabled). The transmission operation does not stop by clearing the serial I/O1 enable bit to "0". q Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to "0" (serial I/O disabled), the internal transmission is running (in this case, since pins TxD1, RxD1, SCLK1, and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to "1" at this time, the data during internally shifting is output to the TxD1 pin and an operation failure occurs. q Note 2 (only receive operation is stopped) Clear the receive enable bit to "0" (receive disabled). Rev.4.01 Nov 14, 2003 page 54 of 136 3803/3804 Group 3. SRDY1 output of reception side q Note When signals are output from the SRDY1 pin on the reception side by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY1 output enable bit, and the transmit enable bit to "1" (transmit enabled). 4. Setting serial I/O1 control register again q Note Set the serial I/O1 control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to "0." Clear both the transmit enable bit (TE) and the receive enable bit (RE) to "0" 7. Transmit interrupt request when transmit enable bit is set q Note When using the transmit interrupt, take the following sequence. Set the serial I/O1 transmit interrupt enable bit to "0" (disabled). Set the transmit enable bit to "1". Set the serial I/O1 transmit interrupt request bit to "0" after 1 or more instruction has executed. Set the serial I/O1 transmit interrupt enable bit to "1" (enabled). q Reason When the transmit enable bit is set to "1", the transmit buffer empty flag and the transmit shift register shift completion flag are also set to "1". Therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is generated and the transmit interrupt request bit is set at this point. Set the bits 0 to 3 and bit 6 of the serial I/O control register Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to "1" Can be set with the LDM instruction at the same time 5. Data transmission control with referring to transmit shift register completion flag q Note After the transmit data is written to the transmit buffer register, the transmit shift register completion flag changes from "1" to "0" with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. Transmission control when external clock is selected q Note When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to "1" at "H" of the SCLK1 input level. Also, write data to the transmit buffer register at "H" of the SCLK1 input level. Rev.4.01 Nov 14, 2003 page 55 of 136 3803/3804 Group Serial I/O2 The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O2, the transmitter and the receiver must use the same clock. If the internal clock is used, transfer is started by a write signal to the serial I/O2 register. b7 b0 Serial I/O2 control register (SIO2CON : address 001D16) Internal synchronous clock selection bits b2 b1 b0 [Serial I/O2 Control Register (SIO2CON)] 001D16 The serial I/O2 control register contains eight bits which control various serial I/O2 functions. 0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode) 0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode) 0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode) 0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode) 1 1 0: f(XIN)/128 (f(XCIN)/128 in low-speed mode) 1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode) Serial I/O2 port selection bit 0: I/O port 1: SOUT2,SCLK2 signal output SRDY2 output enable bit 0: I/O port 1: SRDY2 signal output Transfer direction selection bit 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit 0: External clock 1: Internal clock P51/SOUT2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Fig. 45 Structure of serial I/O2 control register 1/8 1/16 Divider Internal synchronous clock selection bits f(XIN) (f(XCIN) in low-speed mode) 1/32 1/64 1/128 1/256 Data bus P53 latch "0 " P53/SRDY2 Serial I/O2 synchronous clock selection bit "1" Synchronization circuit SCLK2 SRDY2 "1 " SRDY2 output enable bit "0" External clock P52 latch "0 " P52/SCLK2 "1" Serial I/O2 port selection bit Serial I/O counter 2 (3) Serial I/O2 interrupt request P51 latch "0 " P51/SOUT2 "1 " Serial I/O2 port selection bit P50/SIN2 Serial I/O2 register (8) Address 001F16 Fig. 46 Block diagram of serial I/O2 Rev.4.01 Nov 14, 2003 page 56 of 136 3803/3804 Group Transfer clock (Note 1) Serial I/O2 register write signal (Note 2) Serial I/O2 output SOUT2 Serial I/O2 input SIN2 D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal SRDY2 Serial I/O2 interrupt request bit set Notes 1: When the internal clock is selected as the transfer clock, the divide ratio of f(XIN), or f(XCIN) in low-speed mode, can be selected by setting bits 0 to 2 of the serial I/O2 control register. 2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high impedance after transfer completion. Fig. 47 Timing of serial I/O2 Rev.4.01 Nov 14, 2003 page 57 of 136 3803/3804 Group Serial I/O3 Serial I/O3 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O3 mode can be selected by setting the serial I/O3 mode selection bit of the serial I/O3 control register (bit 6 of address 003216) to "1". For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. Data bus Serial I/O3 control register Address 003216 Address 003016 Receive buffer register 3 Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit P34/RXD3 Receive shift register 3 Shift clock P36/SCLK3 BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 P37/SRDY3 F/F Falling-edge detector Serial I/O3 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 3 1/4 Address 002F16 Clock control circuit Shift clock Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O3 status register Address 003116 P35/TXD3 Transmit shift register 3 Transmit buffer register 3 Address 003016 Data bus Fig. 48 Block diagram of clock synchronous serial I/O3 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD3 Serial input RxD3 D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Receive enable signal SRDY3 Write pulse to receive/transmit buffer register (address 003016) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection TBE = 1 TSC = 0 Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O3 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" . Fig. 49 Operation of clock synchronous serial I/O3 Rev.4.01 Nov 14, 2003 page 58 of 136 3803/3804 Group (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O3 mode selection bit of the serial I/O3 control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in a memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Data bus Address 003016 Receive buffer register 3 OE Character length selection bit ST detector 7 bits Receive shift register 3 Serial I/O3 control register Address 003216 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 P34/RXD3 8 bits PE FE SP detector Clock control circuit Serial I/O3 synchronous clock selection bit P36/SCLK3 BRG count source selection bit Frequency division ratio 1/(n+1) f(XIN) Baud rate generator 3 (f(XCIN) in low-speed mode) Address 002F16 1/4 ST/SP/PA generator 1/16 P35/TXD3 Character length selection bit Transmit buffer register 3 Transmit shift register 3 UART3 control register Address 003316 Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O3 status register Address 003116 Address 003016 Data bus Fig. 50 Block diagram of UART serial I/O3 Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 TBE=0 TBE=1 TSC=1] Serial output TXD3 ST D0 D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) SP ST D0 D1 ] SP Generated at 2nd bit in 2-stop-bit mode Receive buffer read signal RBF=0 RBF=1 RBF=1 Serial input RXD3 ST D0 D1 SP ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes "1," can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O3 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1." 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0. Fig. 51 Operation of UART serial I/O3 Rev.4.01 Nov 14, 2003 page 59 of 136 3803/3804 Group [Serial I/O3 Control Register (SIO3CON)] 003216 The serial I/O3 control register consists of eight control bits for the serial I/O3 function. [UART3 Control Register (UART3CON)] 003316 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer, and one bit (bit 4) which is always valid and sets the output structure of the P35/TXD3 pin. [Serial I/O3 Status Register (SIO3STS)] 003116 The read-only serial I/O3 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O3 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O3 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O3 enable bit SIOE (bit 7 of the serial I/O3 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O3 status register are initialized to "0" at reset, but if the transmit enable bit (bit 4) of the serial I/O3 control register has been set to "1", the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1". [Transmit Buffer Register 3/Receive Buffer Register 3 (TB3/RB3)] 003016 The transmit buffer register 3 and the receive buffer register 3 are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0". [Baud Rate Generator 3 (BRG3)] 002F16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. Rev.4.01 Nov 14, 2003 page 60 of 136 3803/3804 Group b7 b0 Serial I/O3 status register (SIO3STS : address 003116) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read) b7 b0 Serial I/O3 control register (SIO3CON : address 003216) BRG count source selection bit (CSS) 0: f(XIN) (f(XCIN) in low-speed mode) 1: f(XIN)/4 (f(XCIN)/4 in low-speed mode) Serial I/O3 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY3 output enable bit (SRDY) 0: P37 pin operates as normal I/O pin 1: P37 pin operates as SRDY3 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O3 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O3 enable bit (SIOE) 0: Serial I/O disabled (pins P34 to P37 operate as normal I/O pins) 1: Serial I/O enabled (pins P34 to P37 operate as serial I/O pins) b7 b0 UART3 control register (UART3CON : address 003316) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P35/TXD3 P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return "1" when read) Fig. 52 Structure of serial I/O3 control registers Rev.4.01 Nov 14, 2003 page 61 of 136 3803/3804 Group s Notes concerning serial I/O3 1. Notes when selecting clock synchronous serial I/O 1.1 Stop of transmission operation q Note Clear the serial I/O3 enable bit and the transmit enable bit to "0" (serial I/O and transmit disabled). q Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O3 enable bit is cleared to "0" (serial I/O disabled), the internal transmission is running (in this case, since pins TxD3, RxD3, SCLK3, and SRDY3 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O enable bit is set to "1" at this time, the data during internally shifting is output to the TxD3 pin and an operation failure occurs. 1.2 Stop of receive operation q Note Clear the receive enable bit to "0" (receive disabled), or clear the serial I/O3 enable bit to "0" (serial I/O disabled). 1.3 Stop of transmit/receive operation q Note Clear both the transmit enable bit and receive enable bit to "0" (transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data transmission and reception cannot be stopped.) q Reason In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to "0" (transmit disabled). Also, the transmission circuit is not initialized by clearing the serial I/O3 enable bit to "0" (serial I/O disabled) (refer to 1.1). 2. Notes when selecting clock asynchronous serial I/O 2.1 Stop of transmission operation q Note Clear the transmit enable bit to "0" (transmit disabled). The transmission operation does not stop by clearing the serial I/O3 enable bit to "0". q Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O3 enable bit is cleared to "0" (serial I/O disabled), the internal transmission is running (in this case, since pins TxD3, RxD3, SCLK3, and SRDY3 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O3 enable bit is set to "1" at this time, the data during internally shifting is output to the TxD3 pin and an operation failure occurs. 2.2 Stop of receive operation q Note Clear the receive enable bit to "0" (receive disabled). 2.3 Stop of transmit/receive operation q Note 1 (only transmission operation is stopped) Clear the transmit enable bit to "0" (transmit disabled). The transmission operation does not stop by clearing the serial I/O3 enable bit to "0". q Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O3 enable bit is cleared to "0" (serial I/O disabled), the internal transmission is running (in this case, since pins TxD3, RxD3, SCLK3, and SRDY3 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O3 enable bit is set to "1" at this time, the data during internally shifting is output to the TxD3 pin and an operation failure occurs. q Note 2 (only receive operation is stopped) Clear the receive enable bit to "0" (receive disabled). Rev.4.01 Nov 14, 2003 page 62 of 136 3803/3804 Group 3. SRDY3 output of reception side q Note When signals are output from the SRDY3 pin on the reception side by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY3 output enable bit, and the transmit enable bit to "1" (transmit enabled). 4. Setting serial I/O3 control register again q Note Set the serial I/O3 control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to "0." Clear both the transmit enable bit (TE) and the receive enable bit (RE) to "0" 7. Transmit interrupt request when transmit enable bit is set q Note When using the transmit interrupt, take the following sequence. Set the serial I/O3 transmit interrupt enable bit to "0" (disabled). Set the transmit enable bit to "1". Set the serial I/O3 transmit interrupt request bit to "0" after 1 or more instruction has executed. Set the serial I/O3 transmit interrupt enable bit to "1" (enabled). q Reason When the transmit enable bit is set to "1", the transmit buffer empty flag and the transmit shift register shift completion flag are also set to "1". Therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is generated and the transmit interrupt request bit is set at this point. Set the bits 0 to 3 and bit 6 of the serial I/O3 control register Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to "1" Can be set with the LDM instruction at the same time 5. Data transmission control with referring to transmit shift register completion flag q Note After the transmit data is written to the transmit buffer register, the transmit shift register completion flag changes from "1" to "0" with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. Transmission control when external clock is selected q Note When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to "1" at "H" of the SCLK3 input level. Also, write data to the transmit buffer register at "H" of the SCLK input level. Rev.4.01 Nov 14, 2003 page 63 of 136 3803/3804 Group PULSE WIDTH MODULATION (PWM) The 3803/3804 group has PWM functions with an 8-bit resolution, based on a signal that is the clock input XIN or that clock input divided by 2 or the clock input XCIN or that clock input divided by 2 in low-speed mode. PWM Operation When bit 0 (PWM enable bit) of the PWM control register is set to "1", operation starts by initializing the PWM output circuit, and pulses are output starting at an "H". If the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made. Data Setting The PWM output pin also functions as port P56. Set the PWM period by the PWM prescaler, and set the "H" term of output pulse by the PWM register. If the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 (n+1) / f(XIN) = 31.875 (n+1) s (when f(XIN) = 8 MHz) Output pulse "H" term = PWM period m / 255 = 0.125 (n+1) m s (when f(XIN) = 8 MHz) 31.875 m (n+1) s 255 PWM output T = [31.875 (n+1)] s m: Contents of PWM register n : Contents of PWM prescaler T : PWM period (when f(XIN) = 8 MHz, count source is f(XIN)) Fig. 53 Timing of PWM period Data bus PWM prescaler pre-latch PWM register pre-latch Transfer control circuit PWM prescaler latch Count source selection bit XIN or PWM register latch "0" "1" Port P56 PWM register PWM prescaler XCIN 1/2 Port P56 latch PWM enable bit Fig. 54 Block diagram of PWM function Rev.4.01 Nov 14, 2003 page 64 of 136 3803/3804 Group b7 b0 PWM control register (PWMCON : address 002B16) PWM function enable bit 0: PWM disabled 1: PWM enabled Count source selection bit 0: f(XIN) 1: f(XIN)/2 Not used (return "0" when read) Fig. 55 Structure of PWM control register A B C B= C T2 T PWM output T PWM register write signal T T2 (Changes "H" term from "A" to "B".) PWM prescaler write signal (Changes PWM period from "T" to "T2".) When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change. Fig. 56 PWM output timing when PWM register or PWM prescaler is changed Rev.4.01 Nov 14, 2003 page 65 of 136 3803/3804 Group A-D CONVERTER [A-D Conversion Register 1, 2 (AD1, AD2)] 003516, 003816 The A-D conversion register is a read-only register that stores the result of an A-D conversion. When reading this register during an A-D conversion, the previous conversion result is read. Bit 7 of the A-D conversion register 2 is the conversion mode selection bit. When this bit is set to "0," the A-D converter becomes the 10-bit A-D mode. When this bit is set to "1," that becomes the 8-bit A-D mode. The conversion result of the 8-bit A-D mode is stored in the A-D conversion register 1. As for 10-bit A-D mode, not only 10-bit reading but also only high-order 8-bit reading of conversion result can be performed by selecting the reading procedure of the A-D conversion registers 1, 2 after A-D conversion is completed (in Figure 58). As for 10-bit A-D mode, the 8-bit reading inclined to MSB is performed when reading the A-D converter register 1 after A-D conversion is started; and when the A-D converter register 1 is read after reading the A-D converter register 2, the 8-bit reading inclined to LSB is performed. Channel Selector The channel selector selects one of ports P67/AN7 to P60/AN0 or P07/AN15 to P00/AN8, and inputs the voltage to the comparator. Comparator and Control Circuit The comparator and control circuit compares an analog input voltage with the comparison voltage, and then stores the result in the A-D conversion registers 1, 2. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to "1". Note that because the comparator consists of a capacitor coupling, set f(XIN) to 500 kHz or more during an A-D conversion. b7 b0 AD/DA control register (ADCON : address 003416) Analog input pin selection bits 1 b2 b1 b0 [AD/DA Control Register (ADCON)] 003416 The AD/DA control register controls the A-D conversion process. Bits 0 to 2 and bit 4 select a specific analog input pin. Bit 3 signals the completion of an A-D conversion. The value of this bit remains at "0" during an A-D conversion, and changes to "1" when an A-D conversion ends. Writing "0" to this bit starts the A-D conversion. 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0: P60/AN0 or P00/AN8 1: P61/AN1 or P01/AN9 0: P62/AN2 or P02/AN10 1: P63/AN3 or P03/AN11 0: P64/AN4 or P04/AN12 1: P65/AN5 or P05/AN13 0: P66/AN6 or P06/AN14 1: P67/AN7 or P07/AN15 AD conversion completion bit 0: Conversion in progress 1: Conversion completed Analog input pin selection bit 2 0: AN0 to AN7 side 1: AN8 to AN15 side Not used (returns "0" when read) DA1 output enable bit 0: DA1 output disabled 1: DA1 output enabled DA2 output enable bit 0: DA2 output disabled 1: DA2 output enabled Comparison Voltage Generator The comparison voltage generator divides the voltage between VREF and AVSS into 1024, and that outputs the comparison voltage in the 10-bit A-D mode (256 division in 8-bit A-D mode). The A-D converter successively compares the comparison voltage Vref in each mode, dividing the VREF voltage (see below), with the input voltage. * 10-bit A-D mode (10-bit reading) Vref = VREF n (n = 0-1023) 1024 * 10-bit A-D mode (8-bit reading) Vref = VREF n (n = 0-255) 256 * 8-bit A-D mode Vref = VREF (n-0.5) (n = 1-255) 256 =0 (n = 0) Fig. 57 Structure of AD/DA control register 10-bit reading (Read address 003816 before 003516) b7 A-D conversion register 2 0 (AD2: address 003816) A-D conversion register 1 (AD1: address 003516) b7 b0 b9 b8 b0 b7 b6 b5 b4 b3 b2 b1 b0 Note : Bits 2 to 6 of address 003816 become "0" at reading. 8-bit reading (Read only address 003516) b7 b0 A-D conversion register 1 b9 b8 b7 b6 b5 b4 b3 b2 (AD1: address 003516) Fig. 58 Structure of 10-bit A-D mode reading Rev.4.01 Nov 14, 2003 page 66 of 136 3803/3804 Group Data bus AD/DA control register (Address 003416) b7 b0 4 P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 A-D control circuit A-D conversion register 2 A-D conversion register 1 10 Resistor ladder AD converter interrupt request Comparator (Address 003816) (Address 003516) Channel selector VREF AVSS Fig. 59 Block diagram of A-D converter Rev.4.01 Nov 14, 2003 page 67 of 136 3803/3804 Group D-A CONVERTER The 3803/3804 group has two internal D-A converters (DA1 and DA2) with 8-bit resolution. The D-A conversion is performed by setting the value in each D-A conversion register. The result of D-A conversion is output from the DA1 or DA2 pin by setting the DA output enable bit to "1". When using the D-A converter, the corresponding port direction register bit (P30/DA1 or P31/DA2) must be set to "0" (input status). The output analog voltage V is determined by the value n (decimal notation) in the D-A conversion register as follows: V = VREF n/256 (n = 0 to 255) Where VREF is the reference voltage. At reset, the D-A conversion registers are cleared to "0016", and the DA output enable bits are cleared to "0", and the P30/DA1 and P31/DA2 pins become high impedance. The DA output does not have buffers. Accordingly, connect an external buffer when driving a low-impedance load. D-A1 conversion register (8) DA1 output enable bit P30/DA1 Data bus R-2R resistor ladder D-A2 conversion register (8) DA2 output enable bit P31/DA2 R-2R resistor ladder Fig. 60 Block diagram of D-A converter "0" DA1 output enable bit R P30/DA1 "1" MSB D-A1 conversion register "0" "1" 2R R R R R R R 2R 2R 2R 2R 2R 2R 2R 2R LSB AVSS VREF Fig. 61 Equivalent connection circuit of D-A converter (DA1) Rev.4.01 Nov 14, 2003 page 68 of 136 3803/3804 Group WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and an 8-bit watchdog timer H. Watchdog Timer Initial Value Watchdog timer L is set to "FF16" and watchdog timer H is set to "FF16" by writing to the watchdog timer control register (address 001E16) or at a reset. Any write instruction that causes a write signal can be used, such as the STA, LDM, CLB, etc. Data can only be written to bits 6 and 7 of the watchdog timer control register. Regardless of the value written to bits 0 to 5, the above-mentioned value will be set to each timer. When bit 6 of the watchdog timer control register is kept at "0", the STP instruction is enabled. When that is executed, both the clock and the watchdog timer stop. Count re-starts at the same time as the release of stop mode (Note). The watchdog timer does not stop while a WIT instruction is executed. In addition, the STP instruction is disabled by writing "1" to this bit again. When the STP instruction is executed at this time, it is processed as an undefined instruction, and an internal reset occurs. Once a "1" is written to this bit, it cannot be programmed to "0" again. The following shows the period between the write execution to the watchdog timer control register and the underflow of watchdog timer H. Bit 7 of the watchdog timer control register is "0": when XCIN = 32.768 kHz; 32 s when XIN = 16 MHz; 65.536 ms Bit 7 of the watchdog timer control register is "1": when XCIN = 32.768 kHz; 125 ms when XIN = 16 MHz; 256 s Note: The watchdog timer continues to count even while waiting for a stop release. Therefore, make sure that watchdog timer H does not underflow during this period. Watchdog Timer Operations The watchdog timer stops at reset and a countdown is started by the writing to the watchdog timer control register. An internal reset occurs when watchdog timer H underflows. The reset is released after its release time. After the release, the program is restarted from the reset vector address. Usually, write to the watchdog timer control register by software before an underflow of the watchdog timer H. The watchdog timer does not function if the watchdog timer control register is not written to at least once. "FF16" is set when watchdog timer control register is written to. Watchdog timer L (8) 1/16 "00" "01" Data bus "FF16" is set when watchdog timer control register is written to. Watchdog timer H (8) XCIN "10" Main clock division ratio selection bits (Note) XIN "0" "1" Watchdog timer H count source selection bit STP instruction disable bit STP instruction Reset circuit Reset release time waiting Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. Internal reset RESET Fig. 62 Block diagram of Watchdog timer b7 b0 Watchdog timer control register (WDTCON : address 001E16) Watchdog timer H (for read-out of high-order 6 bit) STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(XIN)/16 or f(XCIN)/16 Fig. 63 Structure of Watchdog timer control register Rev.4.01 Nov 14, 2003 page 69 of 136 3803/3804 Group MULTI-MASTER I2C-BUS INTERFACE The 3804 group has the multi-master interface. The multi-master I2C-BUS interface is a serial communications circuit, conforming to the Philips I2C-BUS data transfer format. This interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. Figure 64 shows a block diagram of the multi-master I2C-BUS interface and Table 10 lists the multi-master I2 C-BUS interface functions. This multi-master I2C-BUS interface consists of the I2C slave address registers 0 to 2, the I2 C data shift register, the I 2C clock control register, the I2C control register, the I2C status register, the I2C START/STOP condition control register, the I2C special mode control register, the I2C special mode status register, and other control circuits. When using the multi-master I 2C-BUS interface, set 1 MHz or more to the internal clock . I2C-BUS Table 10 Multi-master I2C-BUS interface functions Item Function In conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode In conformity with Philips I2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 kHz to 400 kHz (at = 4 MHz) Format Communication mode SCL clock frequency System clock = f(XIN)/2 (high-speed mode) = f(XIN)/8 (middle-speed mode) Interrupt generating circuit Interrupt request signal (SCL, SDA, IRQ) b7 I2C slave address registers 0 to 2 b0 SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB S0D0-2 Address comparator Serial data (SDA) Noise elimination circuit Data control circuit b7 I2C data shift register S0 Interrupt generating circuit Interrupt request signal (I2CIRQ) b0 b7 MST TRX BB PIN b0 AL AAS AD0 LRB SIS SIP SSC4 SSC3 SSC2 SSC1 SSC0 S2D I2C START/STOP condition control register AL circuit S1 Internal data bus I2C status register BB circuit Serial clock (SCL) Noise elimination circuit Clock control circuit b7 ACK b0 ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 BIT MODE b7 SPCF PIN2 b0 AAS2 AAS1 AAS0 S2 I2C clock control register Clock division System clock () S3 I2C special mode status register b7 b7 TISS TSEL 10 BIT S AD b0 PIN2 HD PIN2 IN HSLAD ACK I CON b0 ALS ES0 BC2 BC1 BC0 SPCFL S1D I2C control register Bit counter S3D I2 C special mode control register Fig. 64 Block diagram of multi-master I2C-BUS interface : Purchase of MITSUBISHI ELECTRIC CORPORATIONS I2C components conveys a license under the Philips I2C Patent Rights to use these components an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Rev.4.01 Nov 14, 2003 page 70 of 136 3803/3804 Group [I2C Data Shift Register (S0)] 001116 The I2C data shift register (S0: address 001116) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL, and each time one-bit data is output, the data of this register are shifted by one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL, and each time one-bit data is input, the data of this register are shifted by one bit to the left. The minimum 2 cycles of the internal clock are required from the rising of the SCL until input to this register. The I2C data shift register is in a write enable status only when the I2C-BUS interface enable bit (ES0 bit) of the I2C control register (S1D: address 001416) is "1". The bit counter is reset by a write instruction to the I2C data shift register. When both the ES0 bit and the MST bit of the I2C status register (S1: address 001316) are "1," the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ES0 bit value. b7 b0 I2C slave address register 0 (S0D0: address 0FF716) I2C slave address register 1 (S0D1: address 0FF816) I2C slave address register 2 (S0D2: address 0FF916) Read/write bit Slave address SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB Fig. 65 Structure of I2C slave address registers 0 to 2 [I2C Slave Address Registers 0 to 2 (S0D0 to S0D2)] 0FF716 to 0FF916 The I2C slave address registers 0 to 2 (S0D0 to S0D2: addresses 0FF716 to 0FF916) consists of a 7-bit slave address and a read/ write bit. In the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the START condition is detected. *Bit 0: Read/write bit (RWB) This is not used in the 7-bit addressing mode. In the 10-bit addressing mode, set RWB to "0" because the first address data to be received is compared with the contents (SAD6 to SAD0 + RWB) of the I2C slave address registers 0 to 2. When 2-byte address data match slave address, a 7-bit slave address which is received after restart condition has detected and R/W data can be matched by setting "1" to RWB with software. The RWB is cleared to "0" automatically when the stop condition is detected. *Bits 1 to 7: Slave address (SAD0-SAD6) These bits store slave addresses. Regardless of the 7-bit addressing mode or the 10-bit addressing mode, the address data transmitted from the master is compared with these bits' contents. Rev.4.01 Nov 14, 2003 page 71 of 136 3803/3804 Group [I2C Clock Control Register (S2)] 001516 The I2C clock control register (S2: address 001516) is used to set ACK control, SCL mode and SCL frequency. *Bits 0 to 4: SCL frequency control bits (CCR0-CCR4) These bits control the SCL frequency. Refer to Table 11. *Bit 5: SCL mode specification bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to "0," the standard clock mode is selected. When the bit is set to "1," the high-speed clock mode is selected. When connecting the bus of the high-speed mode I 2C bus standard (maximum 400 kbits/s), use 8 MHz or more oscillation frequency f(XIN) in the high-speed mode (2 division clock). *Bit 6: ACK bit (ACK BIT) This bit sets the SDA status when an ACK clock is generated. When this bit is set to "0," the ACK return mode is selected and SDA goes to "L" at the occurrence of an ACK clock. When the bit is set to "1," the ACK non-return mode is selected. The SDA is held in the "H" status at the occurrence of an ACK clock. However, when the slave address agree with the address data in the reception of address data at ACK BIT = "0," the SDA is automatically made "L" (ACK is returned). If there is a disagreement between the slave address and the address data, the SDA is automatically made "H" (ACK is not returned). ACK clock: Clock for acknowledgment b7 ACK A CK B IT b0 F AST MODE CCR4 CCR3 CCR2 CCR1 CCR0 I2C clock control register (S2 : address 001516) SCL frequency control bits Refer to Table 11. SCL mode specification bit 0 : Standard clock mode 1 : High-speed clock mode ACK bit 0 : ACK is returned. 1 : ACK is not returned. ACK clock bit 0 : No ACK clock 1 : ACK clock Fig. 66 Structure of I2C clock control register Table 11 Set values of I2 C clock control register and SCL frequency Setting value of CCR4-CCR0 CCR4 CCR3 CCR2 CCR1 CCR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 SCL frequency (at = 4 MHz, unit : kHz) (Note 1) Standard clock High-speed clock mode mode Setting disabled Setting disabled Setting disabled - (Note 2) - (Note 2) 100 83.3 500/CCR value (Note 3) 17.2 16.6 16.1 Setting disabled Setting disabled Setting disabled 333 250 400 (Note 3) 166 1000/CCR value (Note 3) 34.5 33.3 32.3 *Bit 7: ACK clock bit (ACK) This bit specifies the mode of acknowledgment which is an acknowledgment response of data transfer. When this bit is set to "0," the no ACK clock mode is selected. In this case, no ACK clock occurs after data transmission. When the bit is set to "1," the ACK clock mode is selected and the master generates an ACK clock each completion of each 1-byte data transfer. The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (makes SDA "H") and receives the ACK bit generated by the data receiving device. Note: Do not write data into the I2C clock control register during transfer. If data is written during transfer, the I 2C clock generator is reset, so that data cannot be transferred normally. ... ... ... ... 0 1 1 1 1 1 1 1 1 1 1 1 Notes 1: Duty of SCL output is 50 %. The duty becomes 35 to 45 % only when the high-speed clock mode is selected and CCR value = 5 (400 kHz, at = 4 MHz). "H" duration of the clock fluctuates from -4 to +2 machine cycles in the standard clock mode, and fluctuates from -2 to +2 machine cycles in the high-speed clock mode. In the case of negative fluctuation, the frequency does not increase because "L" duration is extended instead of "H" duration reduction. These are values when SCL synchronization by the synchronous function is not performed. CCR value is the decimal notation value of the SCL frequency control bits CCR4 to CCR0. 2: Each value of SCL frequency exceeds the limit at = 4 MHz or more. When using these setting value, use of 4 MHz or less. 3: The data formula of SCL frequency is described below: /(8 CCR value) Standard clock mode /(4 CCR value) High-speed clock mode (CCR value 5) /(2 CCR value) High-speed clock mode (CCR value = 5) Do not set 0 to 2 as CCR value regardless of frequency. Set 100 kHz (max.) in the standard clock mode and 400 kHz (max.) in the high-speed clock mode to the SCL frequency by setting the SCL frequency control bits CCR4 to CCR0. Rev.4.01 Nov 14, 2003 page 72 of 136 ... 1 0 1 3803/3804 Group [I2C Control Register (S1D)] 001416 The I2C control register (S1D: address 001416) controls data communication format. *Bits 0 to 2: Bit counter (BC0-BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. The I2C interrupt request signal occurs immediately after the number of count specified with these bits (ACK clock is added to the number of count when ACK clock is selected by ACK clock bit (bit 7 of S2, address 001516) have been transferred, and BC0 to BC2 are returned to "0002". Also when a START condition is received, these bits become "0002" and the address data is always transmitted and received in 8 bits. *Bit 3: I2C interface enable bit (ES0) This bit enables to use the multi-master I2C-BUS interface. When this bit is set to "0," the use disable status is provided, so that the SDA and the SCL become high-impedance. When the bit is set to "1," use of the interface is enabled. When ES0 = "0," the following is performed. * PIN = "1," BB = "0" and AL = "0" are set (which are bits of the I2C status register, S1, at address 001316 ). * Writing data to the I2C data shift register (S0: address 001116) is disabled. *Bit 4: Data format selection bit (ALS) This bit decides whether or not to recognize slave addresses. When this bit is set to "0," the addressing format is selected, so that address data is recognized. When a match is found between a slave address and address data as a result of comparison or when a general call (refer to "I 2C Status Register," bit 1) is received, transfer processing can be performed. When this bit is set to "1," the free data format is selected, so that slave addresses are not recognized. *Bit 5: Addressing format selection bit (10BIT SAD) This bit selects a slave address specification format. When this bit is set to "0," the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I2C slave address registers 0 to 2 are compared with address data. When this bit is set to "1," the 10-bit addressing format is selected, and all the bits of the I2C slave address registers 0 to 2 are compared with address data. *Bit 7: I2C-BUS interface pin input level selection bit (TISS) This bit selects the input level of the SCL and SDA pins of the multi-master I2C-BUS interface. b7 TISS 10 BIT SAD b0 ALS ES0 BC2 BC1 BC0 I2C control register (S1D : address 001416) Bit counter (Number of transmit/receive bits) b2 b1 b0 0 0 0:8 0 0 1:7 0 1 0:6 0 1 1:5 1 0 0:4 1 0 1:3 1 1 0:2 1 1 1:1 I2C-BUS interface enable bit 0 : Disabled 1 : Enabled Data format selection bit 0 : Addressing format 1 : Free data format Addressing format selection bit 0 : 7-bit addressing format 1 : 10-bit addressing format Not used (return "0" when read) I2C-BUS interface pin input level selection bit 0 : SMBUS input 1 : CMOS input Fig. 67 Structure of I2C control register Rev.4.01 Nov 14, 2003 page 73 of 136 3803/3804 Group [I2C Status Register (S1)] 001316 The I2C status register (S1: address 001316) controls the I2C-BUS interface status. The low-order 4 bits are read-only bits and the high-order 4 bits can be read out and written to. Set "00002" to the low-order 4 bits, because these bits become the reserved bits at writing. *Bit 0: Last receive bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to "0." If ACK is not returned, this bit is set to "1." Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from "1" to "0" by executing a write instruction to the I 2C data shift register (S0: address 001116). *Bit 1: General call detecting flag (AD0) When the ALS bit is "0", this bit is set to "1" when a general call whose address data is all "0" is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to "0" by detecting the STOP condition or START condition, or reset. General call: The master transmits the general call address "0016" to all slaves. The AL bit is set to "0" in one of the following conditions: *Executing a write instruction to the I2C data shift register (S0: address 001116) *When the ES0 bit is "0" *At reset Arbitration lost :The status in which communication as a master is disabled. *Bit 4: SCL pin low hold bit (PIN) *Bit 2: Slave address comparison flag (AAS) This flag indicates a comparison result of address data when the ALS bit is "0". In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to "1" in one of the following conditions: * The address data immediately after occurrence of a START condition agrees with the slave address stored in the high-order 7 bits of the I2C slave address register. * A general call is received. In the slave receive mode, when the 10-bit addressing format is selected, this bit is set to "1" with the following condition: * When the address data is compared with the I 2 C slave address register (8 bits consisting of slave address and RWB bit), the first bytes agree. This bit is set to "0" by executing a write instruction to the I2C data shift register (S0: address 001116) when ES0 is set to "1" or reset. *Bit 3: Arbitration lost detecting flag (AL) In the master transmission mode, when the SDA is made "L" by any other device, arbitration is judged to have been lost, so that this bit is set to "1." At the same time, the TRX bit is set to "0," so that immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to "0." The arbitration lost can be detected only in the master transmission mode. When arbitration is lost during slave address transmission, the TRX bit is set to "0" and the reception mode is set. Consequently, it becomes possible to detect the agreement of its own slave address and address data transmitted by another master device. This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the PIN bit changes from "1" to "0." At the same time, an interrupt request signal occurs to the CPU. The PIN bit is set to "0" in synchronization with a falling of the last clock (including the ACK clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling of the PIN bit. When the PIN bit is "0," the SCL is kept in the "0" state and clock generation is disabled. Figure 69 shows an interrupt request signal generating timing chart. The PIN bit is set to "1" in one of the following conditions: * Executing a write instruction to the I2C data shift register (S0: address 001116). (This is the only condition which the prohibition of the internal clock is released and data can be communicated except for the start condition detection.) * When the ES0 bit is "0" * At reset * When writing "1" to the PIN bit by software The PIN bit is set to "0" in one of the following conditions: * Immediately after completion of 1-byte data transmission (including when arbitration lost is detected) * Immediately after completion of 1-byte data reception * In the slave reception mode, with ALS = "0" and immediately after completion of slave address agreement or general call address reception * In the slave reception mode, with ALS = "1" and immediately after completion of address data reception *Bit 5: Bus busy flag (BB) This bit indicates the status of use of the bus system. When this bit is set to "0," this bus system is not busy and a START condition can be generated. The BB flag is set/reset by the SCL, SDA pins input signal regardless of master/slave. This flag is set to "1" by detecting the START condition, and is set to "0" by detecting the STOP condition. The condition of these detecting is set by the START/STOP condition setting bits (SSC4-SSC0) of the I 2C START/STOP condition control register (S2D: address 001616). When the ES0 bit of the I2C control register (bit 3 of S1D, address 001416) is "0" or reset, the BB flag is set to "0." For the writing function to the BB flag, refer to the sections "START Condition Generating Method" and "STOP Condition Generating Method" described later. Rev.4.01 Nov 14, 2003 page 74 of 136 3803/3804 Group *Bit 6: Communication mode specification bit (transfer direction specification bit: TRX) This bit decides a direction of transfer for data communication. When this bit is "0," the reception mode is selected and the data of a transmitting device is received. When the bit is "1," the transmission mode is selected and address data and control data are output onto the SDA in synchronization with the clock generated on the SCL. This bit is set/reset by software and hardware. About set/reset by hardware is described below. This bit is set to "1" by hardware when all the following conditions are satisfied: * When ALS is "0" * In the slave reception mode or the slave transmission mode * When the R/W bit reception is "1" This bit is set to "0" in one of the following conditions: * When arbitration lost is detected. * When a STOP condition is detected. * When writing "1" to this bit by software is invalid by the START condition duplication preventing function (Note). * With MST = "0" and when a START condition is detected. * With MST = "0" and when ACK non-return is detected. * At reset *Bit 7: Communication mode specification bit (master/slave specification bit: MST) This bit is used for master/slave specification for data communication. When this bit is "0," the slave is specified, so that a START condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. When this bit is "1," the master is specified and a START condition and a STOP condition are generated. Additionally, the clocks required for data communication are generated on the SCL. This bit is set to "0" in one of the following conditions. * Immediately after completion of the byte which has lost arbitration when arbitration lost is detected * When a STOP condition is detected. * Writing "1" to this bit by software is invalid by the START condition duplication preventing function (Note). * At reset Note: START condition duplication preventing function The MST, TRX, and BB bits is set to "1" at the same time after confirming that the BB flag is "0" in the procedure of a START condition occurrence. However, when a START condition by another master device occurs and the BB flag is set to "1" immediately after the contents of the BB flag is confirmed, the START condition duplication preventing function makes the writing to the MST and TRX bits invalid. The duplication preventing function becomes valid from the rising of the BB flag to reception completion of slave address. b7 b0 I2C status register (S1 : address 001316) Last receive bit (Note) 0 : Last bit = "0" 1 : Last bit = "1" General call detecting flag (Note) 0 : No general call detected 1 : General call detected Slave address comparison flag (Note) 0 : Address disagreement 1 : Address agreement Arbitration lost detecting flag (Note) 0 : Not detected 1 : Detected SCL pin low hold bit 0 : SCL pin low hold 1 : SCL pin low release Bus busy flag 0 : Bus free 1 : Bus busy Communication mode specification bits 00 : Slave receive mode 01 : Slave transmit mode 10 : Master receive mode 11 : Master transmit mode MST TRX BB PIN AL AAS AD0 LRB Note: These bits and flags can be read out, but cannot be written. Write "0" to these bits at writing. Fig. 68 Structure of I2C status register SCL PIN I2CIRQ Fig. 69 Interrupt request signal generating timing Rev.4.01 Nov 14, 2003 page 75 of 136 3803/3804 Group START Condition Generating Method When writing "1" to the MST, TRX, and BB bits of the I2C status register (S1: address 001316) at the same time after writing the slave address to the I2C data shift register (S0: address 001116) with the condition in which the ES0 bit of the I2C control register (S1D: address 001416) is "1" and the BB flag is "0", a START condition occurs. After that, the bit counter becomes "0002" and an SCL for 1 byte is output. The START condition generating timing is different in the standard clock mode and the high-speed clock mode. Refer to Figure 70, the START condition generating timing diagram, and Table 12, the START condition generating timing table. STOP Condition Generating Method When the ES0 bit of the I 2 C control register (S1D: address 001416) is "1," write "1" to the MST and TRX bits, and write "0" to the BB bit of the I2C status register (S1: address 001316) simultaneously. Then a STOP condition occurs. The STOP condition generating timing is different in the standard clock mode and the high-speed clock mode. Refer to Figure 71, the STOP condition generating timing diagram, and Table 13, the STOP condition generating timing table. I2C status register write signal SCL Setup time Hold time I2C status register write signal SCL SDA Setup time Hold time SDA Fig. 71 STOP condition generating timing diagram Table 13 STOP condition generating timing table Standard clock mode High-speed clock mode Item 5.0 s (20 cycles) 3.0 s (12 cycles) Setup time Hold time 4.5 s (18 cycles) 2.5 s (10 cycles) Note: Absolute time at = 4 MHz. The value in parentheses denotes the number of cycles. Fig. 70 START condition generating timing diagram Table 12 START condition generating timing table Standard clock mode High-speed clock mode Item Setup time Hold time 5.0 s (20 cycles) 5.0 s (20 cycles) 2.5 s (10 cycles) 2.5 s (10 cycles) Note: Absolute time at = 4 MHz. The value in parentheses denotes the number of cycles. Rev.4.01 Nov 14, 2003 page 76 of 136 3803/3804 Group START/STOP Condition Detecting Operation The START/STOP condition detection operations are shown in Figures 72, 73, and Table 14. The START/STOP condition is set by the START/STOP condition set bit. The START/STOP condition can be detected only when the input signal of the SCL and SDA pins satisfy three conditions: SCL release time, setup time, and hold time (see Table 14). The BB flag is set to "1" by detecting the START condition and is reset to "0" by detecting the STOP condition. The BB flag set/reset timing is different in the standard clock mode and the high-speed clock mode. Refer to Table 14, the BB flag set/ reset time. Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal "I2CIRQ" occurs to the CPU. SCL release time SCL SDA BB flag Setup time Hold time BB flag set time Fig. 72 START/STOP condition detecting timing diagram SCL release time SCL SDA BB flag Setup time Hold time BB flag reset time Table 14 START condition/STOP condition detecting conditions Standard clock mode High-speed clock mode SCL release time Setup time Hold time BB flag set/ reset time SSC value + 1 cycle (6.25 s) 4 cycles (1.0 s) SSC value + 1 cycle < 4.0 s (3.125 s) 2 cycles (0.5 s) 2 SSC value + 1 cycle < 4.0 s (3.125 s) 2 cycles (0.5 s) 2 SSC value -1 + 2 cycles (3.375 s) 3.5 cycles (0.875 s) 2 Fig. 73 STOP condition detecting timing diagram Note: Unit : Cycle number of internal clock SSC value is the decimal notation value of the START/STOP condition set bits SSC4 to SSC0. Do not set "0" or an odd number to SSC value. The value in parentheses is an example when the I2C START/ STOP condition control register is set to "1816" at = 4 MHz. Rev.4.01 Nov 14, 2003 page 77 of 136 3803/3804 Group [I2C START/STOP Condition Control Register (S2D)] 001616 The I2C START/STOP condition control register (S2D: address 001616) controls START/STOP condition detection. *Bits 0 to 4: START/STOP condition set bits (SSC4-SSC0) SCL release time, setup time, and hold time change the detection condition by value of the main clock divide ratio selection bit and the oscillation frequency f(XIN) because these time are measured by the internal system clock. Accordingly, set the proper value to the START/STOP condition set bits (SSC4 to SSC0) in considered of the system clock frequency. Refer to Table 14. Do not set "000002" or an odd number to the START/STOP condition set bits (SSC4 to SSC0). Refer to Table 15, the recommended set value to START/STOP condition set bits (SSC4-SSC0) for each oscillation frequency. *Bit 5: SCL/SDA interrupt pin polarity selection bit (SIP) An interrupt can occur when detecting the falling or rising edge of the SCL or SDA pin. This bit selects the polarity of the SCL or SDA pin interrupt pin. *Bit 6: SCL/SDA interrupt pin selection bit (SIS) This bit selects the pin of which interrupt becomes valid between the SCL pin and the SDA pin. Note: When changing the setting of the SCL/SDA interrupt pin polarity selection bit, the SCL/SDA interrupt pin selection bit, or the I2C-BUS interface enable bit ES0, the SCL/SDA interrupt request bit may be set. When selecting the SCL/SDA interrupt source, disable the interrupt before the SCL/SDA interrupt pin polarity selection bit, the SCL/ SDA interrupt pin selection bit, or the I2C-BUS interface enable bit ES0 is set. Reset the request bit to "0" after setting these bits, and enable the interrupt. b7 b0 SIS SIP SSC4 SSC3 SSC2 SSC1 SSC0 I2C START/STOP condition control register (S2D : address 001616) START/STOP condition set bits SCL/SDA interrupt pin polarity selection bit 0 : Falling edge active 1 : Rising edge active SCL/SDA interrupt pin selection bit 0 : SDA valid 1 : SCL valid Not used (Fix this bit to "0".) Fig. 74 Structure of I2C START/STOP condition control register Table 15 Recommended set value to START/STOP condition set bits (SSC4-SSC0) for each oscillation frequency Oscillation frequency f(XIN) (MHz) 8 8 4 2 Main clock divide ratio 2 8 2 2 Internal clock (MHz) 4 1 2 1 START/STOP condition control register XXX11010 XXX11000 XXX00100 XXX01100 XXX01010 XXX00100 SCL release time (s) 6.75 s (27 cycles) 6.25 s (25 cycles) 5.0 s (5 cycles) 6.5 s (13 cycles) 5.5 s (11 cycles) 5.0 s (5 cycles) Setup time (s) 3.5 s (14 cycles) 3.25 s (13 cycles) 3.0 s (3 cycles) 3.5 s (7 cycles) 3.0 s (6 cycles) 3.0 s (3 cycles) Hold time (s) 3.25 s (13 cycles) 3.0 s (12 cycles) 2.0 s (2 cycles) 3.0 s (6 cycles) 2.5 s (5 cycles) 2.0 s (2 cycles) Note: Do not set an odd number to the START/STOP condition set bits (SSC4 to SSC0) and "000002". Rev.4.01 Nov 14, 2003 page 78 of 136 3803/3804 Group [I 2 C Special Mode Status Register (S3)] 001216 The I2C special mode status register (S3: address 001216) consists of the flags indicating I2C operating state in the I2C special mode, which is set by the I2C special mode control register (S3D: address 001716). The stop condition flag is valid in all operating modes. *Bit 0: Slave address 0 comparison flag (AAS0) Bit 1: Slave address 1 comparison flag (AAS1) Bit 2: Slave address 2 comparison flag (AAS2) These flags indicate a comparison result of address data. These flags are valid only when the slave address control bit (MSLAD) is "1". In the 7-bit addressing format of the slave reception mode, the respective slave address i (i = 0, 1, 2) comparison flags corresponding to the I2C slave address registers 0 to 2 are set to "1" when an address data immediately after an occurrence of a START condition agrees with the high-order 7-bit slave address stored in the I2C slave address registers 0 to 2 (addresses 0FF716 to 0FF916). In the 10-bit addressing format of the slave mode, the respective slave address i (i = 0, 1, 2) comparison flags corresponding to the I2C slave address registers are set to "1" when an address data is compared with the 8 bits consisting of the slave address stored in the I2C slave address registers 0 to 2 and the RWB bit, and the first byte agrees. These flags are initialized to "0" at reset, when the slave address control bit (MSLAD) is "0", or when writing data to the I 2C data shift register (S0: address 001116). *Bit 5: SCL pin low hold 2 flag (PIN2) When the ACK interrupt control bit (ACKICON) and the ACK clock bit (ACK) are "1", this flag is set to "0" in synchronization with the falling of the data's last SCL clock, just before the ACK clock. The SCL pin is simultaneously held low, and the I2C interrupt request occurs. This flag is initialized to "1" at reset, when the ACK interrupt control bit (ACKICON) is "0", or when writing "1" to the SCL pin low hold 2 flag set bit (PIN2IN). The SCL pin is held low when either the SCL pin low hold bit (PIN) or the SCL pin low hold 2 flag (PIN2) becomes "0". The low hold state of the SCL pin is released when both the SCL pin low hold bit (PIN) and the SCL pin low hold 2 flag (PIN2) are "1". *Bit 7: Stop condition flag (SPCF) This flag is set to "1" when a STOP condition occurs. This flag is initialized to "0" at reset, when the I 2C-BUS interface enable bit (ES0) is "0", or when writing "1" to the STOP condition flag clear bit (SPFCL). b7 SP CF PIN2 b0 AA S2 AA S1 AA S0 I2C special mode status register (S3 : address 001216) Slave address 0 comparison flag 0 : Address disagreement 1 : Address agreement Slave address 1 comparison flag 0 : Address disagreement 1 : Address agreement Slave address 2 comparison flag 0 : Address disagreement 1 : Address agreement Not used (return "0" when read) Not used (return "0" when read) SCL pin low hold 2 flag 0 : SCL pin low hold 1 : SCL pin low release (Note) Not used (return "0" when read) STOP condition flag 0 : No detection 1 : Detection Note: In order that the low hold state of the SCL pin may release, it is necessary that the SCL pin low hold 2 flag and the SCL pin low hold bit (PIN) are "1" simultaneously. Fig. 75 Structure of I2C special mode status register Rev.4.01 Nov 14, 2003 page 79 of 136 3803/3804 Group [I 2C Special Mode Control Register (S3D)] 001716 The I2C special mode control register (S3D: address 001716) controls special functions such as occurrence timing of reception interrupt request and extending slave address comparison to 3 bytes. *Bit 1: ACK interrupt control bit (ACKICON) This bit controls the timing of I2C interrupt request occurrence at completion of data receiving due to master reception or slave reception. When this bit is "0", the SCL pin low hold bit (PIN) is set to "0" in synchronization with the falling of the last SCL clock, including the ACK clock. The SCL pin is simultaneously held low, and the I2C interrupt request occurs. When this bit is "1" and the ACK clock bit (ACK) is "1", the SCL pin low hold 2 flag (PIN2) is set to "0" in synchronization with the falling of the data's last SCL clock, just before the ACK clock. The SCL pin is simultaneously held low, and the I2C interrupt request occurs again. The ACK bit can be changed after the contents of data are confirmed by using this function. *Bit 2: I2C slave address control bit (MSLAD) This bit controls a slave address. When this bit is "0", only the I2C slave address register 0 (address 0FF716) becomes valid as a slave address and a read/write bit. When this bit is "1", all of the I2C slave address registers 0 to 2 (addresses 0FF716 to 0FF916) become valid as a slave address and a read/write bit. In this case, when an address data agrees with any one of the I2C slave address registers 0 to 2, the slave address comparison flag (AAS) is set to "1" and the I2C slave address comparison flag corresponding to the agreed I 2 C slave address registers 0 to 2 is also set to "1". *Bit 5: SCL pin low hold 2 flag set bit (PIN2IN) Writing "1" to this bit initializes the SCL pin low hold 2 flag (PIN2) to "1". When writing "0", nothing is generated. *Bit 6: SCL pin low hold set bit (PIN2HD) When the SCL pin low hold bit (PIN) becomes "0", the SCL pin is held low. However, the SCL pin low hold bit (PIN) cannot be set to "0" by software. The SCL pin low hold set bit (PIN2HD) is used to , hold the SCL pin in the low state by software. When writing "1" to this bit, the SCL pin low hold 2 flag (PIN2) becomes "0", and the SCL pin is held low. When writing "0", nothing occurs. *Bit 7: STOP condition flag clear bit (SPFCL) Writing "1" to this bit initializes the STOP condition flag (SPCF) to "0". When writing "0", nothing is generated. b7 SPFCL b0 PIN2PIN2IN HD MSLAD ACKI CON I2C special mode control register (S3D : address 001716) Not used (Fix this bit to "0".) ACK interrupt control bit 0 : At communication completion 1 : At falling of ACK clock and communication completion Slave address control bit 0 : One-byte slave address compare mode 1 : Three-byte slave address compare mode Not used (return "0" when read) Not used (Fix this bit to "0".) SCL pin low hold 2 flag set bit (Notes 1, 2) Writing "1" to this bit initializes the SCL pin low hold 2 flag to "1". SCL pin low hold set bit (Notes 1, 2) When writing "1" to this bit, the SCL pin low hold 2 flag becomes "0" and the SCL pin is held low. STOP condition flag clear bit (Note 2) Writing "1" to this bit initializes the STOP condition flag to "0". Notes 1: Do not write "1" to these bits simultaneously. 2: return "0" when read Fig. 76 Structure of I2C special mode control register Rev.4.01 Nov 14, 2003 page 80 of 136 3803/3804 Group Address Data Communication There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats are described below. 7-bit addressing format To adapt the 7-bit addressing format, set the 10BIT SAD bit of the I2C control register (S1D: address 001416) to "0". The first 7bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the I2 C slave address register. At the time of this comparison, address comparison of the RWB bit of the I2C slave address register is not performed. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 77, (1) and (2). 10-bit addressing format To adapt the 10-bit addressing format, set the 10BIT SAD bit of the I 2C control register (S1D: address 001416) to "1." An address comparison is performed between the first-byte address data transmitted from the master and the 8-bit slave address stored in the I2C slave address register. At the time of this com- parison, an address comparison between the RWB bit of the I2C slave address register and the R/W bit which is the last bit of the address data transmitted from the master is made. In the 10-bit addressing mode, the RWB bit which is the last bit of the address data not only specifies the direction of communication for control data, but also is processed as an address data bit. When the first-byte address data agree with the slave address, the AAS bit of the I2C status register (S1: address 001316) is set to "1." After the second-byte address data is stored into the I2C data shift register (S0: address 001116), perform an address comparison between the second-byte data and the slave address by software. When the address data of the 2 bytes agree with the slave address, set the RWB bit of the I2C slave address register to "1" by software. This processing can make the 7-bit slave address and R/W data agree, which are received after a RESTART condition is detected, with the value of the I2C slave address register. For the data transmission format when the 10-bit addressing format is selected, refer to Figure 77, (3) and (4). (1) A master-transmitter transmits data to a slave-receiver S Slave address R/W 7 bits "0" A Data 1 to 8 bits A Data 1 to 8 bits A/A P (2) A master-receiver receives data from a slave-transmitter S Slave address R/W 7 bits "1" A Data 1 to 8 bits A Data 1 to 8 bits A P (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address S Slave address R/W 1st 7 bits 7 bits "0" A Slave address 2nd bytes 8 bits A Data 1 to 8 bits A Data 1 to 8 bits A/A P (4) A master-receiver receives data from a slave-transmitter with a 10-bit address S Slave address R/W 1st 7 bits 7 bits "0" A Slave address 2nd bytes 8 bits A Sr Slave address R/W 1st 7 bits 7 bits "1" A Data 1 to 8 bits A Data 1 to 8 bits A P S : START condition A : ACK bit Sr : Restart condition P : STOP condition R/W : Read/Write bit : Master to slave : Slave to master Fig. 77 Address data communication format Rev.4.01 Nov 14, 2003 page 81 of 136 3803/3804 Group Example of Master Transmission An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. Set a slave address in the high-order 7 bits of the I2C slave address register and "0" into the RWB bit. Set the ACK return mode and SCL = 100 kHz by setting "8516" in the I2C clock control register (S2: address 001516). Set "0016" in the I2C status register (S1: address 001316) so that transmission/reception mode can become initializing condition. Set a communication enable status by setting "0816" in the I2C control register (S1D: address 001416). Confirm the bus free condition by the BB flag of the I2C status register (S1: address 001316). Set the address data of the destination of transmission in the high-order 7 bits of the I 2C data shift register (S0: address 001116) and set "0" in the least significant bit. Set "F016" in the I2C status register (S1: address 001316) to generate a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occur. Set transmit data in the I 2C data shift register (S0: address 001116). At this time, an SCL and an ACK clock automatically occur. When transmitting control data of more than 1 byte, repeat step . Set "D016" in the I2C status register (S1: address 001316) to generate a STOP condition if ACK is not returned from slave reception side or transmission ends. Example of Slave Reception An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-return mode and using the addressing format is shown below. Set a slave address in the high-order 7 bits of the I2C slave address register and "0" in the RWB bit. Set the no ACK clock mode and SCL = 400 kHz by setting "2516" in the I2C clock control register (S2: address 001516). Set "0016" in the I2C status register (S1: address 001316) so that transmission/reception mode can become initializing condition. Set a communication enable status by setting "0816" in the I2C control register (S1D: address 001416). When a START condition is received, an address comparison is performed. *When all transmitted addresses are "0" (general call): AD0 of the I2C status register (S1: address 001316) is set to "1" and an interrupt request signal occurs. * When the transmitted addresses agree with the address set in : AAS of the I2C status register (S1: address 001316) is set to "1" and an interrupt request signal occurs. * In the cases other than the above AD0 and AAS of the I2C status register (S1: address 001316) are set to "0" and no interrupt request signal occurs. Set dummy data in the I 2 C data shift register (S0: address 001116). When receiving control data of more than 1 byte, repeat step . When a STOP condition is detected, the communication ends. Rev.4.01 Nov 14, 2003 page 82 of 136 3803/3804 Group sPrecautions when using multi-master I2CBUS interface (1) Read-modify-write instruction The precautions when the read-modify-write instruction such as SEB, CLB etc. is executed for each register of the multi-master I2C-BUS interface are described below. * I2C data shift register (S0: address 001116) When executing the read-modify-write instruction for this register during transfer, data may become a value not intended. * I2C slave address registers 0 to 2 (S0D0 to S0D2: addresses 0FF716 to0FF916) When the read-modify-write instruction is executed for this register at detecting the STOP condition, data may become a value not intended. It is because H/W changes the read/write bit (RWB) at the above timing. * I2C status register (S1: address 001316) Do not execute the read-modify-write instruction for this register because all bits of this register are changed by H/W. * I2C control register (S1D: address 001416) When the read-modify-write instruction is executed for this register at detecting the START condition or at completing the byte transfer, data may become a value not intended. Because H/W changes the bit counter (BC0-BC2) at the above timing. * I2C clock control register (S2: address 001516) The read-modify-write instruction can be executed for this register. * I 2 C START/STOP condition control register (S2D: address 001616) The read-modify-write instruction can be executed for this register. (2) START condition generating procedure using multi-master 1. Procedure example (The necessary conditions of the generating procedure are described as the following 2 to 5. : : LDA -- SEI BBS 5, S1, BUSBUSY BUSFREE: STA S0 LDM #$F0, S1 CLI : : BUSBUSY: CLI : : (Taking out of slave address value) (Interrupt disabled) (BB flag confirming and branch process) (Writing of slave address value) (Trigger of START condition generating) (Interrupt enabled) 5. Disable interrupts during the following three process steps: * BB flag confirming * Writing of slave address value * Trigger of START condition generating When the condition of the BB flag is bus busy, enable interrupts immediately. (3) RESTART condition generating procedure 1. Procedure example (The necessary conditions of the generating procedure are described as the following 2 to 4.) Execute the following procedure when the PIN bit is "0." : : LDM #$00, S1 (Select slave receive mode) LDA -- (Taking out of slave address value) SEI (Interrupt disabled) STA S0 (Writing of slave address value) LDM #$F0, S1 (Trigger of RESTART condition generating) CLI (Interrupt enabled) : : 2. Select the slave receive mode when the PIN bit is "0." Do not write "1" to the PIN bit. Neither "0" nor "1" is specified for the writing to the BB bit. The TRX bit becomes "0" and the SDA pin is released. 3. The SCL pin is released by writing the slave address value to the I2C data shift register. 4. Disable interrupts during the following two process steps: * Writing of slave address value * Trigger of RESTART condition generating (4) Writing to I2C status register Do not execute an instruction to set the PIN bit to "1" from "0" and an instruction to set the MST and TRX bits to "0" from "1" simultaneously. It is because it may enter the state that the SCL pin is released and the SDA pin is released after about one machine cycle. Do not execute an instruction to set the MST and TRX bits to "0" from "1" simultaneously when the PIN bit is "1." It is because it may become the same as above. (5) Process of after STOP condition generating Do not write data in the I2C data shift register S0 and the I2C status register S1 until the bus busy flag BB becomes "0" after generating the STOP condition in the master mode. It is because the STOP condition waveform might not be normally generated. Reading to the above registers does not have the problem. (Interrupt enabled) 2. Use "Branch on Bit Set" of "BBS 5, S1, -" for the BB flag confirming and branch process. 3. Use "STA $12, STX $12" or "STY $12" of the zero page addressing instruction for writing the slave address value to the I2C data shift register. 4. Execute the branch instruction of above 2 and the store instruction of above 3 continuously shown the above procedure example. Rev.4.01 Nov 14, 2003 page 83 of 136 3803/3804 Group RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an "L" level for 16 cycles or more of XIN. Then the RESET pin is returned to an "H" level (the power source voltage should be between 2.7 V and 5.5 V, and the oscillation should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.54 V for VCC of 2.7 V. Poweron Power source voltage 0V Reset input voltage 0V (Note) RESET VCC 0.2VCC Note : Reset release voltage ; Vcc=2.7 V RESET VCC Power source voltage detection circuit Fig. 78 Reset circuit example XIN RESET Internal reset Address ? ? ? ? FFFC FFFD ADH,L Reset address from the vector table. Data ? ? ? ? ADL ADH SYNC XIN: 10.5 to 18.5 clock cycles Notes 1: The frequency relation of f(XIN) and f() is f(XIN)=8 * f(). 2: The question marks (?) indicate an undefined state that depends on the previous state. Fig. 79 Reset sequence Rev.4.01 Nov 14, 2003 page 84 of 136 3803/3804 Group Address Register contents (1) (2) (3) (4) (5) (6) (7) (8) (9) Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 (34) Timer Z (low-order) (TZL) (35) Timer Z (high-order) (TZH) (36) Timer Z mode register (TZM) (37) PWM control register (PWMCON) (38) PWM prescaler (PREPWM) (39) PWM register (PWM) (40) Baud rate generator 3 (BRG3) Address Register contents 002816 002916 002A16 002B16 FF16 FF16 0016 0016 002C16 X X X X X X X X 002D16 X X X X X X X X 002F16 X X X X X X X X (41) Transmit/Receive buffer register 3 (TB3/RB3) 003016 X X X X X X X X (42) Serial I/O3 status register (SIO3STS) (43) Serial I/O3 control register (SIO3CON) (44) UART3 control register (SIO3CON) (45) AD/DA control register (ADCON) (46) A-D conversion register 1 (AD1) (47) D-A1 conversion register (DA1) (48) D-A2 conversion register (DA2) (49) A-D conversion register 2 (AD2) (50) Interrupt source selection register (INTSEL) (51) Interrupt edge selection register (INTEDGE) (52) CPU mode register (CPUM) (53) Interrupt request register 1 (IREQ1) (54) Interrupt request register 2 (IREQ2) (55) Interrupt control register 1 (ICON1) (56) Interrupt control register 2 (ICON2) (57) Port P0 pull-up control register (PULL0) (58) Port P1 pull-up control register (PULL1) (59) Port P2 pull-up control register (PULL2) (60) Port P3 pull-up control register (PULL3) (61) Port P4 pull-up control register (PULL4) (62) Port P5 pull-up control register (PULL5) (63) Port P6 pull-up control register (PULL6) (64) Flash memory control register (FCON) (65) Flash command register (FCMD) (66) Processor status register (67) Program counter 003116 1 0 0 0 0 0 0 0 003216 0016 (10) Port P4 direction register (P4D) (11) Port P5 (P5) (12) Port P5 direction register (P5D) (13) Port P6 (P6) (14) Port P6 direction register (P6D) (15) (16) Timer 12, X count source selection register (T12XCSS) Timer Y, Z count source selection register (TYZCSS) 003316 1 1 1 0 0 0 0 0 003416 0 0 0 0 1 0 0 0 003516 X X X X X X X X 003616 003716 0016 0016 000E16 0 0 1 1 0 0 1 1 000F16 0 0 1 1 0 0 1 1 001016 0016 003816 0 0 0 0 0 0 X X 003916 003A16 0016 0016 (17) MISRG (18) Transmit/Receive buffer register 1 (TB1/RB1) (19) Serial I/O1 status register (SIO1STS) (20) Serial I/O1 control register (SIO1CON) (21) UART1 control register (UART1CON) (22) Baud rate generator 1 (BRG1) (23) Serial I/O2 control register (SIO2CON) (24) Watchdog timer control register (WDTCON) (25) Serial I/O2 register (SIO2) (26) Prescaler 12 (PRE12) (27) Timer 1 (T1) (28) Timer 2 (T2) (29) Timer XY mode register (TM) (30) Prescaler X (PREX) (31) Timer X (TX) (32) Prescaler Y (PREY) (33) Timer Y (TY) 001816 X X X X X X X X 001916 1 0 0 0 0 0 0 0 001A16 0016 003B16 0 1 0 0 1 0 0 0 003C16 003D16 003E16 003F16 0FF016 0FF116 0FF216 0FF316 0FF416 0FF516 0FF616 0FFE16 0FFF16 (PS) (PCH) (PCL) 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 X XXXX1 XX FFFD16 contents FFFC16 contents 001B16 1 1 1 0 0 0 0 0 001C16 X X X X X X X X 001D16 0016 001E16 0 0 1 1 1 1 1 1 001F16 X X X X X X X X 002016 002116 002216 002316 002416 002516 002616 002716 FF16 0116 FF16 0016 FF16 FF16 FF16 FF16 Note : X : Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set. Fig. 80 Internal status at reset (3803 group) Rev.4.01 Nov 14, 2003 page 85 of 136 3803/3804 Group Address Register contents (1) (2) (3) (4) (5) (6) (7) (8) (9) Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 (41) Timer Z (low-order) (TZL) (42) Timer Z (high-order) (TZH) (43) Timer Z mode register (TZM) (44) PWM control register (PWMCON) (45) PWM prescaler (PREPWM) (46) PWM register (PWM) (47) Baud rate generator 3 (BRG3) Address Register contents 002816 002916 002A16 002B16 FF16 FF16 0016 0016 002C16 X X X X X X X X 002D16 X X X X X X X X 002F16 X X X X X X X X (48) Transmit/Receive buffer register 3 (TB3/RB3) 003016 X X X X X X X X (49) Serial I/O3 status register (SIO3STS) (50) Serial I/O3 control register (SIO3CON) (51) UART3 control register (SIO3CON) (52) AD/DA control register (ADCON) (53) A-D conversion register 1 (AD1) (54) D-A1 conversion register (DA1) (55) D-A2 conversion register (DA2) (56) A-D conversion register 2 (AD2) (57) Interrupt source selection register (INTSEL) (58) Interrupt edge selection register (INTEDGE) (59) CPU mode register (CPUM) (60) Interrupt request register 1 (IREQ1) (61) Interrupt request register 2 (IREQ2) (62) Interrupt control register 1 (ICON1) (63) Interrupt control register 2 (ICON2) (64) Port P0 pull-up control register (PULL0) (65) Port P1 pull-up control register (PULL1) (66) Port P2 pull-up control register (PULL2) (67) Port P3 pull-up control register (PULL3) (68) Port P4 pull-up control register (PULL4) (69) Port P5 pull-up control register (PULL5) (70) Port P6 pull-up control register (PULL6) (71) I2C slave address register 0 (S0D0) 003116 1 0 0 0 0 0 0 0 003216 0016 (10) Port P4 direction register (P4D) (11) Port P5 (P5) (12) Port P5 direction register (P5D) (13) Port P6 (P6) (14) Port P6 direction register (P6D) (15) (16) Timer 12, X count source selection register (T12XCSS) Timer Y, Z count source selection register (TYZCSS) 003316 1 1 1 0 0 0 0 0 003416 0 0 0 0 1 0 0 0 003516 X X X X X X X X 003616 003716 0016 0016 000E16 0 0 1 1 0 0 1 1 000F16 0 0 1 1 0 0 1 1 001016 0016 003816 0 0 0 0 0 0 X X 003916 003A16 0016 0016 (17) MISRG (18) I 2C data shift register (S0) 001116 X X X X X X X X 001216 0 0 1 0 0 0 0 0 001316 0 0 0 1 0 0 0 X 001416 001516 0016 0016 (19) I2C special mode status register (S3) (20) I2C status register (S1) (21) I2C control register (S1D) (22) I2C clock control register (S2) 003B16 0 1 0 0 1 0 0 0 003C16 003D16 003E16 003F16 0FF016 0FF116 0FF216 0FF316 0FF416 0FF516 0FF616 0FF716 0FF816 0FF916 0FFE16 0FFF16 (PS) (PCH) (PCL) 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 X XXXX1 XX FFFD16 contents FFFC16 contents (23) I2C START/STOP condition control register (S2D)001616 0 0 0 1 1 0 1 0 (24) I2C special mode control register (S3D) (25) Transmit/Receive buffer register 1 (TB1/RB1) (26) Serial I/O1 status register (SIO1STS) (27) Serial I/O1 control register (SIO1CON) (28) UART1 control register (UART1CON) (29) Baud rate generator 1 (BRG1) (30) Serial I/O2 control register (SIO2CON) (31) Watchdog timer control register (WDTCON) (32) Serial I/O2 register (SIO2) (33) Prescaler 12 (PRE12) (34) Timer 1 (T1) (35) Timer 2 (T2) (36) Timer XY mode register (TM) (37) Prescaler X (PREX) (38) Timer X (TX) (39) Prescaler Y (PREY) (40) Timer Y (TY) 001716 0016 001816 X X X X X X X X 001916 1 0 0 0 0 0 0 0 001A16 0016 001B16 1 1 1 0 0 0 0 0 001C16 X X X X X X X X 001D16 0016 001E16 0 0 1 1 1 1 1 1 001F16 X X X X X X X X 002016 002116 002216 002316 002416 002516 002616 002716 FF16 0116 FF16 0016 FF16 FF16 FF16 FF16 (72) I2C slave address register 1 (S0D1) (73) I2C slave address register 2 (S0D3) (74) Flash memory control register (FCON) (75) Flash command register (FCMD) (76) Processor status register (77) Program counter Note : X : Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set. Fig. 81 Internal status at reset (3804 group) Rev.4.01 Nov 14, 2003 page 86 of 136 3803/3804 Group CLOCK GENERATING CIRCUIT The 3803/3804 group has two built-in oscillation circuits: main clock XIN-XOUT oscillation circuit and sub clock XCIN-XCOUT oscillation circuit. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. Immediately after power on, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. Oscillation Control (1) Stop mode If the STP instruction is executed, the internal clock stops at an "H" level, and XIN and XCIN oscillators stop. When the oscillation stabilizing time set after STP instruction released bit is "0," the prescaler 12 is set to "FF16" and timer 1 is set to "0116." When the oscillation stabilizing time set after STP instruction released bit is "1," set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1. After STP instruction is released, the input of the prescaler 12 is connected to count source which had set at executing the STP instruction, and the output of the prescaler 12 is connected to timer 1. Set the timer 1 interrupt enable bit to disabled ("0") before executing the STP instruction. Oscillator restarts when an external interrupt is received, but the internal clock is not supplied to the CPU (remains at "H") until timer 1 underflows. The internal clock is supplied for the first time, when timer 1 underflows. Therefore make sure not to set the timer 1 interrupt request bit to "1" before the STP instruction stops the oscillator. When the oscillator is restarted by reset, apply "L" level to the RESET pin until the oscillation is stable since a wait time will not be generated. Frequency Control (1) Middle-speed mode The internal clock is the frequency of XIN divided by 8. After reset is released, this mode is selected. (2) High-speed mode The internal clock is half the frequency of XIN. (3) Low-speed mode The internal clock is half the frequency of XCIN. (2) Wait mode (4) Low power dissipation mode The low power consumption operation can be realized by stopping the main clock XIN in low-speed mode. To stop the main clock, set bit 5 of the CPU mode register to "1." When the main clock XIN is restarted (by setting the main clock stop bit to "0"), set sufficient time for oscillation to stabilize. If the WIT instruction is executed, the internal clock stops at an "H" level, but the oscillator does not stop. The internal clock restarts when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. sNote *If you switch the mode between middle/high-speed and lowspeed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub clock to stabilize, especially immediately after power on and at returning from stop mode. When switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3f(XCIN). *When using the quartz-crystal oscillator of high frequency, such as 16 MHz etc., it may be necessary to select a specific oscillator with the specification demanded. Rev.4.01 Nov 14, 2003 page 87 of 136 3803/3804 Group XCIN Rf XCOUT Rd CCOUT XIN XOUT CCIN CIN COUT Fig. 82 Ceramic resonator circuit XCIN XCOUT Open XIN XOUT Open External oscillation circuit VCC VSS External oscillation circuit VCC VSS Fig. 83 External clock input circuit Rev.4.01 Nov 14, 2003 page 88 of 136 3803/3804 Group XCIN XCOUT "1" "0" Port XC switch bit XIN XOUT Main clock division ratio selection bits (Note 1) Low-speed mode Divider Prescaler 12 Timer 1 Reset or STP instruction (Note 2) Main clock division ratio selection bits (Note 1) Middle-speed mode 1/2 High-speed or middle-speed mode 1/4 High-speed or low-speed mode Main clock stop bit Timing (internal clock) Q S R STP instruction WIT instruction SQ R QS R STP instruction Reset Reset Interrupt disable flag l Interrupt request Notes 1: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. When low-speed mode is selected, set port Xc switch bit (b4) to "1". 2: f(XIN)/16 is supplied as the count source to the prescaler 12 at reset. The count source before executing the STP instruction is supplied as the count source at executing STP instruction. 3: When bit 0 of MISRG is "0", timer 1 is set "0116" and prescaler 12 is set "FF16" automatically. When bit 0 of MISRG is "1", set the appropriate value to them in accordance with oscillation stabilizing time required by the using oscillator because nothing is automatically set into timer 1 and prescaler 12. Fig. 84 System clock generating circuit block diagram (Single-chip mode) Rev.4.01 Nov 14, 2003 page 89 of 136 3803/3804 Group Reset Middle-speed mode (f()=1 MHz) CM7=0 CM6=1 CM5=0(8 MHz oscillating) CM4=0(32 kHz stopped) CM6 "1""0" High-speed mode (f()=4 MHz) CM7=0 CM6=0 CM5=0(8 MHz oscillating) CM4=0(32 kHz stopped) CM " 0" "1 M6 " C " "1 4 " "0 C "0 M4 CM " "1 6 " 1" " "0 " CM4 "1""0" Middle-speed mode (f()=1 MHz) CM7=0 CM6=1 CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating) CM6 "1""0" High-speed mode (f()=4 MHz) CM7=0 CM6=0 CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating) CM7=1 CM6=0 CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating) CM7 "1""0" Low-speed mode (f()=16 kHz) C "0 M7 CM " "1 6 "1 " " "0 " CM4 "1""0" b7 b4 CPU mode register (CPUM : address 003B16) CM4 : Port Xc switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function CM5 : Main clock (XIN- XOUT) stop bit 0 : Operating 1 : Stopped CM7, CM6: Main clock division ratio selection bit b7 b6 0 0 : = f(XIN)/2 ( High-speed mode) 0 1 : = f(XIN)/8 (Middle-speed mode) 1 0 : = f(XCIN)/2 (Low-speed mode) 1 1 : Not available CM7=1 CM6=0 CM5=1(8 MHz stopped) CM4=1(32 kHz oscillating) Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.) 2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3 : Timer operates in the wait mode. 4 : When the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 and Timer 1 in middle/high-speed mode. 5 : When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 and Timer 2 in low-speed mode. 6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed mode. 7 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. indicates the internal clock. Fig. 85 State transitions of system clock Rev.4.01 Nov 14, 2003 page 90 of 136 CM5 "1""0" Low-speed mode (f()=16 kHz) 3803/3804 Group FLASH MEMORY MODE The 3803/3804 group has the flash memory mode in addition to the normal operation mode (microcomputer mode). The user can use this mode to perform read, program, and erase operations for the internal flash memory. The 3803/3804 group has three modes the user can choose: the parallel input/output and serial input/output mode, where the flash memory is handled by using the external programmer, and the CPU reprogramming mode, where the flash memory is handled by the central processing unit (CPU). The following explains these modes. Functional Outline (parallel input/output mode) In the parallel input/output mode, the 3803/3804 group allow the user to choose an operation mode between the read-only mode and the read/write mode (software command control mode) depending on the voltage applied to the VPP pin. When VPP = VPPL, the read-only mode is selected, and the user can choose one of three states (e.g., read, output disable, or standby) depending on ___ ___ ___ inputs to the CE, OE, and WE pins. When VPP = VPPH, the read/ write mode is selected, and the user can choose one of four states (e.g., read, output disable, standby, or write) depending on inputs __ __ ___ to the CE, OE, and WE pins. Table 17 shows assignment states of control input and each state. q Read __ The microcomputer enters the read state by driving the CE, and __ ___ OE pins low and the WE pin high; and the contents of memory corresponding to the address to be input to address input pins (A0-A16) are output to the data input/output pins (D0-D7). q Output disable The microcomputer enters the output disable state by driving the __ ___ __ CE pin low and the WE and OE pins high; and the data input/output pins enter the floating state. q Standby __ The microcomputer enters the standby state by driving the CE pin high. the 3803/3804 group is placed in a power-down state consuming only a minimum supply current. At this time, the data input/ output pins enter the floating state. q Write The microcomputer enters the write state by driving the VPP pin ___ __ high (VPP = VPPH) and then the WE pin low when the CE pin is __ low and the OE pin is high. In this state, software commands can be input from the data input/output pins, and the user can choose program or erase operation depending on the contents of this software command. (1) Flash memory mode 1 (parallel I/O mode) The parallel I/O mode can be selected by connecting wires as shown in Figures 86, 87 and supplying power to the VCC and VPP pins. In this mode, the M38039FF/M38049FF operates as an equivalent of MITSUBISHI's CMOS flash memory M5M28F101. However, because the M38039FF/M38049FF's internal memory has a capacity of 60 Kbytes, programming is available for addresses 0100016 to 0FFFF16, and make sure that the data in addresses 0000016 to 00FFF16 and addresses 1000016 to 1FFFF16 are FF16. Note also that the M38039FF/M38049FF does not contain a facility to read out a device identification code by applying a high voltage to address input (A9). Be careful not to erratically set program conditions when using a general-purpose PROM programmer. Table 16 shows the pin assignments when operating in the parallel input/output mode. Table 16 Pin assignments of M38039FF/M38049FF when operating in the parallel input/output mode M38039FF/M38049FF VCC VPP VSS Address input Data I/O __ M5M28F101 VCC VPP VSS A0-A16 D0-D7 __ VCC CNVSS VSS Ports P0, P1, P31 Port P2 P36 P37 P33 CE ___ CE __ OE ___ OE ___ WE WE Table 17 Assignment states of control input and each state Pin Mode Read-only State Read Output disable Standby Read Read/Write Output disable Standby Write Note: x can be VIL or VIH. __ __ ___ CE VIL VIL VIH VIL VIL VIH VIL OE VIL VIH x VIL VIH x VIH WE VIH VIH x VIH VIH x VIL VPP VPPL VPPL VPPL VPPH VPPH VPPH VPPH Data I/O Output Floating Floating Output Floating Floating Input Rev.4.01 Nov 14, 2003 page 91 of 136 3803/3804 Group Table 18 Pin description (flash memory parallel I/O mode) Pin VCC, VSS CNVSS _____ RESET XIN XOUT AVSS VREF P00-P07 P10-P17 P20-P27 P30-P37 Name Power supply VPP input Reset input Clock input Clock output Analog supply input Reference voltage input Address input (A0-A7) Address input (A8-A15) Data I/O (D0-D7) Control signal input Input /Output -- Input Input Input Output -- Input Input Input I/O Input Functions Supply 5 V 10 % to VCC and 0 V to VSS. Supply 5 V 10 % in read-only mode, supply 11.7 V to 12.6 V in read/write mode. Connect to VSS. Connect a ceramic resonator between XIN and XOUT. Connect to VSS. Connect to VSS. Port P0 functions as 8-bit address input (A0-A7). Port P1 functions as 8-bit address input (A8-A15). Function as 8-bit data's I/O pins__ __ (D0-D7). ___ P37, P36 and P33 function as the OE, CE and WE input pins respectively. P31 functions as the A16 input pin. Connect P30 and P32 to VSS. Input "H" or "L" to P34, P35, or keep them open. Connect P44, P46 to VSS. Input "H" or "L" to P40 - P43, P45, P47, or keep them open. Input "H" or "L", or keep them open. Input "H" or "L", or keep them open. P40-P47 P50-P57 P60-P67 Input port P4 Input port P5 Input port P6 Input Input Input Rev.4.01 Nov 14, 2003 page 92 of 136 3803/3804 Group A10 A11 A12 A13 P15 35 P10/INT41 P00/AN8 P01/AN9 P11/INT01 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P02/AN10 P07/AN15 P12 P13 P14 P16 34 A14 41 40 39 43 38 37 44 42 47 46 OE CE P37 P36 P35 P34 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 48 45 36 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P17 A15 A4 A5 A1 A6 A2 A7 A0 A3 A8 A9 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) VSS XOUT XIN P40/INT40/XCOUT P41/INT00/XCIN RESET CNVSS P42/INT1 D0 D1 D2 D3 D4 D5 D6 D7 VSS 1 WE A16 P33/(SCL2) P32/(SDA2) P31/DA2 P30/DA1 VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 VCC M38039FFFP/HP M38049FFFP/HP VPP 10 11 12 13 P45/TXD1 14 P53/SRDY2 P55/CNTR1 P54/CNTR0 P47/SRDY1 P52/SCLK2 P51/SOUT2 P46/SCLK1 P56/PWM P44/RXD1 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P50/SIN2 15 * 1 :: Connect to the ceramic oscillation circuit. * 2 3804 groupthe flash memory pin. indicates Outline 64P6N-A/64P6Q-A Fig. 86 Pin connectionwhen operating in parallel input/output mode (M38039FFFP/HP, M38049FFFP/HP) Rev.4.01 Nov 14, 2003 page 93 of 136 P43/INT2 16 2 6 3 5 7 1 4 8 9 3803/3804 Group Vcc VSS VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1 P46/SCLK1 P45/TXD1 P44/RXD1 P43/INT2 P42/INT1 CNVSS VPP RESET P41/INT00/XCIN P40/INT40/XCOUT XIN 1 XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30/DA1 P31/DA2 P32/(SDA2) P33/(SCL2) P34 P35 P36 P37 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 P10/INT41 P11/INT01 P12 P13 P14 P15 P16 P17 P20/(LED0) P21/(LED1) P22/(LED2) P23/(LED3) P24/(LED4) P25/(LED5) P26/(LED6) P27/(LED7) A16 WE CE OE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D2 D3 D4 D5 D6 D7 Outline 64P4B Fig. 87 Pin connection when operating in parallel input/output mode (M38039FFSP, M38049FFSP) M38039FFSP M38049FFSP * 1 :: Connect to the ceramic oscillation circuit. * 2 3804 groupthe flash memory pin. indicates Rev.4.01 Nov 14, 2003 page 94 of 136 3803/3804 Group Read-only Mode The microcomputer enters the read-only mode by applying VPPL to the VPP pin. In this mode, the user can input the address of a memory location to be read and the control signals at the timing shown in Figure 88, and the M38039FF/M38049FF will output the contents of the user's specified address from data I/O pin to the external. In this mode, the user cannot perform any operation other than read. VIH Address VIL tRC VIH CE VIL ta(CE) VIH OE VIL VIH WE VIL VOH Data VOL Floating ta(OE) tOLZ tCLZ ta(AD) Dout tDH Floating tWRR tDF Valid address Fig. 88 Read timing Read/Write Mode The microcomputer enters the read/write mode by applying VPPH to the VPP pin. In this mode, the user must first input a software command to choose the operation (e. g., read, program, or erase) to be performed on the flash memory (this is called the first cycle), and then input the information necessary for execution of the command (e.g, address and data) and control signals (this is called the second cycle). When this is done, the M38039FF/M38049FF executes the specified operation. Table 19 Software command (Parallel input/output mode) Symbol Read Program Program verify Erase Erase verify Reset Device identification First cycle Address input x x x x Verify address x x Table 19 shows the software commands and the input/output information in the first and the second cycles. The input address is ___ latched internally at the falling edge of the WE input; software commands and other input data are latched internally at the rising ___ edge of the WE input. The following explains each software command. Refer to Figures 89 to 91 for details about the signal input/output timings. Second cycle Data input 0016 4016 C016 2016 A016 FF16 9016 Address input Read address Program address x x x x ADI Data I/O Read data (Output) Program data (Input) Verify data (Output) 2016 (Input) Verify data (Output) FF16 (Input) DDI (Output) Note: ADI = Device identification address : manufacturer's code 0000016, device code 0000116 DDI = Device identification data : manufacturer's code 1C16, device code D016 X can be VIL or VIH. Rev.4.01 Nov 14, 2003 page 95 of 136 3803/3804 Group q Read command The microcomputer enters the read mode by inputting command code "0016" in the first cycle. The command code is latched into ___ the internal command latch at the rising edge of the WE input. When the address of a memory location to be read is input in the second cycle, with control signals input at the timing shown in Figure 89, the M38039FF/M38049FF outputs the contents of the specified address from the data I/O pins to the external. The read mode is retained until any other command is latched into the command latch. Consequently, once the M38039FF/M38049FF enters the read mode, the user can read out the successive memory contents simply by changing the input address and executing the second cycle only. Any command other than the read command must be input beginning from its command code over again each time the user execute it. The contents of the command latch immediately after power-on is 0016. VIH Address VIL tWC VIH CE VIL tCS VIH OE VIL tRRW VIH WE VIL ta(OE) tDS VIH Data VIL tVSC VPPH VPP VPPL 0016 tDH tOLZ tCLZ ta(AD) Dout tDH tWP tWRR tDF tCH ta(CE) tRC Valid address Fig. 89 Timings during reading Rev.4.01 Nov 14, 2003 page 96 of 136 3803/3804 Group q Program command The microcomputer enters the program mode by inputting command code "4016" in the first cycle. The command code is latched ___ into the internal command latch at the rising edge of the WE input. When the address which indicates a program location and data is input in the second cycle, the M38039FF/M38049FF internally ___ latches the address at the falling edge of the WE input and the ___ data at the rising edge of the WE input. The M38039FF/ ___ M38049FF starts programming at the rising edge of the WE input in the second cycle and finishes programming within 10 s as measured by its internal timer. Programming is performed in units of bytes. Note: A programming operation is not completed by executing the program command once. Always be sure to execute a program verify command after executing the program command. When the failure is found in this verification, the user must repeatedly execute the program command until the pass. Refer to Figure 92 for the programming flowchart. q Program verify command The microcomputer enters the program verify mode by inputting command code "C016" in the first cycle. This command is used to verify the programmed data after executing the program command. The command code is latched into the internal command ___ latch at the rising edge of the WE input. When control signals are input in the second cycle at the timing shown in Figure 90, the M38039FF/M38049FF outputs the programmed address's contents to the external. Since the address is internally latched when the program command is executed, there is no need to input it in the second cycle. VIH Address VIL tWC VIH CE VIL tCS tCH VIH OE VIL tRRW tWP VIH WE VIL tDS VIH Data VIL tVSC VPPH VPP VPPL 4016 tDH Program verify Program address tAS tAH Program tCS tCH tCS tCH tWPH tWP tDP tWP tWRR tDS tDS DIN tDH C016 tDH Dout Verify data output Fig. 90 Input/output timings during programming (Verify data is output at the same timing as for read.) Rev.4.01 Nov 14, 2003 page 97 of 136 3803/3804 Group q Erase command The erase command is executed by inputting command code 2016 in the first cycle and command code 2016 again in the second cycle. The command code is latched into the internal command ___ latch at the rising edges of the WE input in the first cycle and in the second cycle, respectively. The erase operation is initiated at ___ the rising edge of the WE input in the second cycle, and the memory contents are collectively erased within 9.5 ms as measured by the internal timer. Note that data 0016 must be written to all memory locations before executing the erase command. Note: An erase operation is not completed by executing the erase command once. Always be sure to execute an erase verify command after executing the erase command. When the failure is found in this verification, the user must repeatedly execute the erase command until the pass. Refer to Figure 92 for the erase flowchart. q Erase verify command The user must verify the contents of all addresses after completing the erase command. The microcomputer enters the erase verify mode by inputting the verify address and command code A016 in the first cycle. The address is internally latched at the fall___ ing edge of the WE input, and the command code is internally ___ latched at the rising edge of the WE input. When control signals are input in the second cycle at the timing shown in Figure 91, the M38039FF/M38049FF outputs the contents of the specified address to the external. Note: If any memory location where the contents have not been erased is found in the erase verify operation, execute the operation of "erase erase verify" over again. In this case, however, the user does not need to write data 0016 to memory locations before erasing. VIH Address VIL tWC VIH CE VIL tCS tCH VIH OE VIL tRRW tWP VIH WE VIL tDS VIH Data VIL tVSC VPPH VPP VPPL tDH tDH 2016 2016 tDS tWPH tWP tDE tCS tCH Erase Erase verify Verify address tAS tAH tCS tCH tWP tWRR tDS A016 Dout Verify data output tDH Fig. 91 Input/output timings during erasing (Verify data is output at the same timing as for read.) Rev.4.01 Nov 14, 2003 page 98 of 136 3803/3804 Group q Reset command The reset command provides a means of stopping execution of the erase or program command safely. If the user inputs command code FF16 in the second cycle after inputting the erase or program command in the first cycle and again input command code FF16 in the third cycle, the erase or program command is disabled (i.e., reset), and the 3803/3804 group is placed in the read mode. If the reset command is executed, the contents of the memory does not change. q Device identification code command By inputting command code 9016 in the first cycle, the user can read out the device identification code. The command code is latched into the internal command latch at the rising edge of the ___ WE input. At this time, the user can read out manufacture's code 1C16 (i.e., MITSUBISHI) by inputting 0000016 to the address input pins in the second cycle; the user can read out device code D016 (i. e., 1M-bit flash memory) by inputting 0000116. These command and data codes are input/output at the same timing as for read. Rev.4.01 Nov 14, 2003 page 99 of 136 3803/3804 Group Program START Erase START VCC = 5 V, VPP = VPPH VCC = 5 V, VPP = VPPH ADRS = first location YES ALL BYTES = 0016 ? NO X=0 WRITE PROGRAM COMMAND WRITE PROGRAM DATA DURATION = 10 s X=X+1 WRITE PROGRAM-VERIFY COMMAND DURATION = 6 s YES X = 25 ? NO FAIL PASS VERIFY BYTE ? PASS NO INC ADRS LAST ADRS ? NO YES WRITE READ COMMAND 0016 FAIL VERIFY BYTE ? FAIL 4016 PROGRAM ALL BYTES = 0016 ADRS = first location DIN X=0 WRITE ERASE COMMAND WRITE ERASE COMMAND DURATION = 9.5 ms X=X+1 WRITE ERASE-VERIFY COMMAND DURATION = 6 s 2016 C016 2016 A016 X = 1000 ? YES PASS VERIFY BYTE ? PASS VERIFY BYTE ? FAIL VPP = VPPL INC ADRS DEVICE PASSED DEVICE FAILED NO LAST ADRS ? YES WRITE READ COMMAND 0016 VPP = VPPL DEVICE PASSED DEVICE FAILED Fig. 92 Programming/Erasing algorithm flow chart Rev.4.01 Nov 14, 2003 page 100 of 136 3803/3804 Group Table 20 DC ELECTRICAL CHARACTERISTICS (Ta = 25 C, VCC = 5 V 10 %, unless otherwise noted) Symbol ISB1 ISB2 ICC1 ICC2 ICC3 IPP1 IPP2 IPP3 VIL VIH VOL VOH1 VOH2 VPPL VPPH "H" output voltage VPP supply voltage (read only) VPP supply voltage (read/write) VCC supply current (at standby) VCC supply current (at read) VCC supply current (at program) VCC supply current (at erase) VPP supply current (at read) VPP supply current (at program) VPP supply current (at erase) "L" input voltage "H" input voltage "L" output voltage IOL = 2.1 mA IOH = -400 A IOH = -100 A 2.4 VCC -0.4 VCC 11.7 12.0 VCC + 1.0 12.6 Parameter Test conditions VCC = 5.5 V, CE = VIH VCC = 5.5 V, __ CE = VCC 0.2 V __ __ Limits Min. Typ. Max. 1 100 15 15 15 10 100 100 30 30 0 2.0 0.8 VCC 0.45 Unit mA A mA mA mA A A A mA mA V V V V V V V VCC = 5.5 V, CE = VIL, tRC = 150 ns, IOUT = 0 mA VPP = VPPH VPP = VPPH 0VPPVCC VCC __ Parameter Limits Min. 150 150 150 55 Max. Unit ns ns ns ns ns ns CE access time __ OE access time __ Output enable time (after CE) __ Output enable time (after OE) Output floating time (after OE) __ __ __ 0 0 35 0 6 ns ns s Output valid time (after CE, OE, address) Write recovery time (before read) Table 22 Read/Write mode Symbol tWC tAS tAH tDS tDH tWRR tRRW tCS tCH tWP tWPH tDP tDE tVSC Write cycle time Address set up time Address hold time Data setup time Data hold time Write recovery time (before read) Read recovery time (before write) __ Parameter Limits Min. 150 0 60 50 10 6 0 20 0 60 20 10 9.5 1 Max. Unit ns ns ns ns ns s s ns ns ns ns s ms s CE setup time __ CE hold time Write pulse width Write pulse waiting time Program time Erase time VPP setup time Note: Read timing of Read/Write mode is same as Read-only mode. Rev.4.01 Nov 14, 2003 page 101 of 136 3803/3804 Group (2) Flash memory mode 2 (serial I/O mode) The flash memory version of the 3803/3804 group has a function to serially input/output the software commands, addresses, and data required for operation on the internal flash memory (e. g., read, program, and erase) using only a few pins. This is called the serial I/O (input/output) mode. This mode can be selected by driving the SDA (serial data input/output), SCLK (serial clock input ), __ and OE pins high after connecting wires as shown in Figures 93, 94 and powering on the VCC pin and then applying VPPH to the VPP pin. In the serial I/O mode, the user can use six types of software commands: read, program, program verify, erase, erase verify and error check. Serial input/output is accomplished synchronously with the clock, beginning from the LSB (LSB first). P00/AN8 P01/AN9 P03/AN11 P10/INT41 P11/INT01 P02/AN10 P04/AN12 P05/AN13 P06/AN14 P07/AN15 P12 P13 P14 P15 35 P16 34 41 40 39 43 38 37 44 42 48 46 OE P37/SRDY3 P36/SCLK3 P35/TXD3 P34/RXD3 P33/(SCL2) P32/(SDA2) P31/DA2 P30/DA1 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 47 45 36 33 32 31 30 29 28 27 26 P17 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) VSS XOUT XIN P40/INT40/XCOUT P41/INT00/XCIN RESET CNVSS P42/INT1 Vpp 1 VSS VCC VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 M38039FFFP/HP M38049FFFP/HP 25 24 23 22 21 20 19 18 17 14 10 11 12 13 P45/TXD1 P44/RXD1 SDA 15 P53/SRDY2 P55/CNTR1 P54/CNTR0 P52/SCLK2 P62/AN2 P61/AN1 P60/AN0 P50/SIN2 P51/SOUT2 P47/SRDY1/CNTR2 Outline 64P6N-A/64P6Q-A Fig. 93 Pin connection when operating in serial I/O mode (M38039FFFP/HP, M38049FFFP/HP) Rev.4.01 Nov 14, 2003 page 102 of 136 BUSY * 1 :: Connect to the ceramic oscillation circuit. * 2 3804 groupthe flash memory pin. indicates SCLK P46/SCLK1 P56/PWM P57/INT3 P43/ INT2 16 2 6 3 5 7 1 4 8 9 3803/3804 Group Vcc VSS VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 BUSY P47/SRDY1/CNTR2 P46/SCLK1 SCLK P45/TXD1 SDA P44/RXD1 P43/INT2 P42/INT1 Vpp CNVSS RESET P41/INT00/XCIN P40/INT40/XCOUT XIN 1 XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30/DA1 P31/DA2 P32/(SDA2) P33/(SCL2) P34/RXD3 P35/TXD3 P36/SCLK3 P37/SRDY3 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 P10/INT41 P11/INT01 P12 P13 P14 P15 P16 P17 P20/(LED0) P21/(LED1) P22/(LED2) P23/(LED3) P24/(LED4) P25/(LED5) P26/(LED6) P27/(LED7) OE * 1 :: Connect to the ceramic oscillation circuit. * 2 3804 groupthe flash memory pin. indicates Outline 64P4B Fig. 94 Pin connection when operating in serial I/O mode (M38039FFSP, M38049FFSP) M38039FFSP M38049FFSP Rev.4.01 Nov 14, 2003 page 103 of 136 3803/3804 Group Table 23 Pin description (flash memory serial I/O mode) Pin VCC, VSS CNVSS _____ Name Power supply VPP input Reset input Clock input Clock output Analog supply input Reference voltage input Input port P0 Input port P1 Input port P2 Input port P3 Control signal input Input port P4 SDA I/O SCLK input BUSY output Input port P5 Input port P6 Input /Output -- Input Input Input Output -- Input Input Input Input Input Input Input I/O Input Output Input Input Supply 11.7 V to 12.6 V. Connect to VSS. Functions Supply 5 V 10 % to VCC and 0 V to VSS. RESET XIN XOUT AVSS VREF P00-P07 P10-P17 P20-P27 P30-P36 P37 P40-P43, P45 P44 P46 P47 P50-P57 P60-P67 Connect a ceramic resonator between XIN and XOUT. Connect to VSS. Input an arbitrary level between the range of VSS and VCC. Input "H" or "L", or keep them open. Input "H" or "L", or keep them open. Input "H" or "L", or keep them open. Input "H" or "L", or keep them open. __ OE input pin Input "H" or "L" to P40 - P43, P45, or keep them open. This pin is for serial data I/O. This pin is for serial clock input. This pin is for BUSY signal output. Input "H" or "L", or keep them open. Input "H" or "L", or keep them open. Rev.4.01 Nov 14, 2003 page 104 of 136 3803/3804 Group Functional Outline (serial I/O mode) In the serial I/O mode, data is transferred synchronously with the clock using serial input/output. The input data is read from the SDA pin into the internal circuit synchronously with the rising edge of the serial clock pulse; the output data is output from the SDA pin synchronously with the falling edge of the serial clock pulse. Data is transferred in units of eight bits. Table 24 Software command (serial I/O mode) Number of transfers First command Command Read Program Program verify Erase Erase verify Error check code input 0016 4016 C016 2016 A016 8016 In the first transfer, the user inputs the command code. This is followed by address input and data input/output according to the contents of the command. Table 24 shows the software commands used in the serial I/O mode. The following explains each software command. Second Third Read address H (Input) Program address H (Input) ---------- ---------- Verify address H (Input) ---------- Fourth Read data (Output) Program data (Input) ---------- ---------- Verify data (Output) ---------- Read address L (Input) Program address L (Input) Verify data (Output) 2016 (Input) Verify address L (Input) Error code (Output) q Read command Input command code 0016 in the first transfer. Proceed and input the low-order 8 bits and the high-order 8 bits of the address and __ pull the OE pin low. When this is done, the 3803/3804 group reads out the contents of the specified address, and then latchs it into __ the internal data latch. When the OE pin is released back high and serial clock is input to the SCLK pin, the read data that has been latched into the data latch is serially output from the SDA pin. tCH SCLK A0 SDA A7 tCH A8 A15 D0 D7 00000000 Command code input (0016) Read address input (L) Read address input (H) tCR tWR tRC Read data output OE Read BUSY "L" Note : When outputting the read data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit). Fig. 95 Timings during reading Rev.4.01 Nov 14, 2003 page 105 of 136 3803/3804 Group q Program command Input command code 4016 in the first transfer. Proceed and input the low-order 8 bits and the high-order 8 bits of the address and then program data. Programming is initiated at the last rising edge of the serial clock during program data transfer. The BUSY pin is driven high during program operation. Programming is completed within 10 s as measured by the internal timer, and the BUSY pin is pulled low. Note : A programming operation is not completed by executing the program command once. Always be sure to execute a program verify command after executing the program command. When the failure is found in the verification, the user must repeatedly execute the program command until the pass in the verification. Refer to Figure 92 for the programming flowchart. tCH SCLK tCH tCH tPC A0 SDA 00000010 Command code input (4016) A7 A8 A15 D0 D7 Program address input (L) Program address input (H) Program data input OE tWP Program BUSY Fig. 96 Timings during programming q Program verify command Input command code C016 in the first transfer. Proceed and drive __ the OE pin low. When this is done, the 3803/3804 group verifyreads the programmed address's contents, and then latchs it into the internal data latch. When the OE pin is released back high and serial clock is input to the SCLK pin, the verify data that has been latched into the data latch is serially output from the SDA pin. __ SCLK D0 SDA 00000011 Command code input (C016) tCRPV OE Verify read BUSY "L" D7 Verify data output tWR tRC Note: When outputting the verify data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit). Fig. 97 Timings during program verify Rev.4.01 Nov 14, 2003 page 106 of 136 3803/3804 Group q Erase command Input command code 2016 in the first transfer and command code 2016 again in the second transfer. When this is done, the 3803/ 3804 group executes an erase command. Erase is initiated at the last rising edge of the serial clock. The BUSY pin is driven high during the erase operation. Erase is completed within 9.5 ms as measured by the internal timer, and the BUSY pin is pulled low. Note that data 0016 must be written to all memory locations before executing the erase command. Note: A erase operation is not completed by executing the erase command once. Always be sure to execute a erase verify command after executing the erase command. When the failure is found in the verification, the user must repeatedly execute the erase command until the pass in the verification. Refer to Figure 92 for the erase flowchart. tCH SCLK tEC SDA 00000100 00000100 Command code input (2016) Command code input (2016) "H" OE twE BUSY Erase Fig. 98 Timings at erasing q Erase verify command The user must verify the contents of all addresses after completing the erase command. Input command code A016 in the first transfer. Proceed and input the low-order 8 bits and the high-order __ 8 bits of the address and pull the OE pin low. When this is done, the 3803/3804 group reads out the contents of the specified ad__ dress, and then latchs it into the internal data latch. When the OE pin is released back high and serial clock is input to the SCLK pin, the verify data that has been latched into the data latch is serially output from the SDA pin. Note: If any memory location where the contents have not been erased is found in the erase verify operation, execute the operation of "erase erase verify" over again. In this case, however, the user does not need to write data 0016 to memory locations before erasing. tCH SCLK A0 SDA A7 tCH A8 A15 D0 D7 00000101 Command code input (A016) Verify address input (L) Verify address input (H) tCREV tWR tRC Verify data output OE Verify read BUSY "L" Note : When outputting the verify data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit). Fig. 99 Timings during erase verify Rev.4.01 Nov 14, 2003 page 107 of 136 3803/3804 Group q Error check command Input command code 8016 in the first transfer, and the 3803/3804 group outputs error information from the SDA pin, beginning at the next falling edge of the serial clock. If the LSB bit of the 8-bit error information is 1, it indicates that a command error has occurred. A command error means that some invalid commands other than commands shown in Table 24 has been input. When a command error occurs, the serial communication circuit sets the corresponding flag and stops functioning to avoid an erroneous programming or erase. When being placed in this state, the serial communication circuit does not accept the subsequent serial clock and data (even including an error check command). Therefore, if the user wants to execute an error check command, temporarily drop the VPP pin input to the VPPL level to terminate the serial input/output mode. Then, place the 3803/3804 group into the serial I/O mode back again. The serial communication circuit is reset by this operation and is ready to accept commands. The error flag alone is not cleared by this operation, so the user can examine the serial communication circuit's error conditions before reset. This examination is done by the first execution of an error check command after the reset. The error flag is cleared when the user has executed the error check command. Because the error flag is undefined immediately after power-on, always be sure to execute the error check command. tCH SCLK E0 SDA 00000001 Command code input (8016) "H" ??????? Error flag output OE BUSY "L" Note: When outputting the error flag, the SDA pin is switched for output at the first falling edge of the serial clock. The SDA pin is placed in the floating state during the period of th(C-E) after the last rising edge of the serial clock (at the 8th bit). Fig. 100 Timings at error checking Rev.4.01 Nov 14, 2003 page 108 of 136 3803/3804 Group DC ELECTRICAL CHARACTERISTICS (Ta = 25 C, VCC = 5 V 10 %, VPP = 11.7 V to 12.6 V, unless otherwise noted) ICC, IPP-relevant standards during read, program, and erase are the same as in the parallel input/output mode. VIH, VIL, VOH, VOL, IIH, and __ IIL for the SCLK, SDA, BUSY, OE pins conform to the microcomputer modes. Table 25 AC Electrical characteristics (Ta = 25 C, VCC = 5 V 10 %, VPP = 11.7 V to 12.6 V, f(XIN) = 10 MHz, unless otherwise noted) Symbol tCH tCR tWR tRC tCRPV tWP tPC tCREV tWE tEC tc(CK) tw(CKH) tw(CKL) tr(CK) tf(CK) td(C-Q) th(C-Q) th(C-E) tsu(D-C) th(C-D) Serial transmission interval Read waiting time after transmission Read pulse width Transfer waiting time after read Waiting time before program verify Programming time Transfer waiting time after programming Waiting time before erase verify Erase time Transfer waiting time after erase SCLK input cycle time SCLK high-level pulse width SCLK low-level pulse width SCLK rise time SCLK fall time SDA output delay time SDA output hold time SDA output hold time (only the 8th bit) SDA input set up time SDA input hold time 500(Note 1) 250 100 100 20 20 0 0 150(Note 3) 250(Note 4) 30 90 90 Parameter Limits Min. 500(Note 1) 500(Note 1) 400(Note 2) 500(Note 1) 6 10 500(Note 1) 6 9.5 Max. Unit ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1: When f(XIN) = 10 MHz or less, calculate the minimum value according to formula 1. 5000 x 106 f(XIN) 2: When f(XIN) = 10 MHz or less, calculate the minimum value according to formula 2. Formula 1 : 4000 x 106 f(XIN) 3: When f(XIN) = 10 MHz or less, calculate the minimum value according to formula 3. Formula 2 : 1500 x 106 f(XIN) 4: When f(XIN) = 10 MHz or less, calculate the minimum value according to formula 4 Formula 3 : Formula 4 : 2500 f(XIN) x 106 AC waveforms tf(CK) tw(CKL) tc(CK) tr(CK) tw(CKH) SCLK th(C-Q) td(C-Q) th(C-E) Test conditions for AC characteristics SDA output * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V tsu(D-C) th(C-D) * Input timing voltage : VIL = 0.2 VCC, VIH = 0.8 VCC SDA input Rev.4.01 Nov 14, 2003 page 109 of 136 3803/3804 Group (3) Flash memory mode 3 (CPU reprogramming mode) The 3803/3804 group has the CPU reprogramming mode where a built-in flash memory is handled by the central processing unit (CPU). In CPU reprogramming mode, the flash memory is handled by writing and reading to/from the flash memory control register (see Figure 101) and the flash command register (see Figure 102). The CNVSS pin is used as the VPP power supply pin in CPU reprogramming mode. It is necessary to apply the power-supply voltage of VPPH from the external to this pin. Whether these operations have been completed or not is judged by checking this flag after each command of erase and the program is executed. Bits 4, 5 of the flash memory control register are the erase/program area select bits. These bits specify an area where erase and program is operated. When the erase command is executed after an area is specified by these bits, only the specified area is erased. Only for the specified area, programming is enabled; for the other areas, programming is disabled. Figure 103 shows the CPU mode register bit configuration in the CPU reprogramming mode. Functional Outline (CPU reprogramming mode) Figure 101 shows the flash memory control register bit configuration. Figure 102 shows the flash command register bit configuration. Bit 0 of the flash memory control register is the CPU reprogramming mode select bit. When this bit is set to "1" and VPPH is applied to the CNVss/VPP pin, the CPU reprogramming mode is selected. Whether the CPU reprogramming mode is realized or not is judged by reading the CPU reprogramming mode monitor flag (bit 2 of the flash memory control register). Bit 1 is a busy flag which becomes "1" during erase and program execution. 7 6 0 5 4 3 0 2 1 0 Flash memory control register (FCON : address 0FFE16) CPU reprogramming mode select bit (Note) 0 : CPU reprogramming mode is invalid. (Normal operation mode) 1 : When applying 0 V to CNVSS/VPP pin, CPU reprogramming mode is invalid. When applying VPPH to CNVSS/VPP pin, CPU reprogramming mode is valid. Erase/Program busy flag 0 : Erase and program are completed or not have been executed. 1 : Erase/program is being executed. CPU reprogramming mode monitor flag 0 : CPU reprogramming mode is invalid. 1 : CPU reprogramming mode is valid. Fix this bit to "0." Erase/Program area select bits 0 0 : Addresses 100016 to FFFF16 (total 60 Kbytes) 0 1 : Addresses 100016 to 7FFF16 (total 28 Kbytes) 1 0 : Addresses 800016 to FFFF16 (total 32 Kbytes) 1 1 : Not available Fix this bit to "0." Not used (returns "0" when read) Note: Bit 0 can be reprogrammed only when 0 V is applied to the CNVSS/VPP pin. Fig. 101 Flash memory control register bit configuration Rev.4.01 Nov 14, 2003 page 110 of 136 3803/3804 Group q CPU reprogramming mode operation procedure The operation procedure in CPU reprogramming mode is described below. < Beginning procedure > Apply 0 V to the CNVss/VPP pin for reset release. Set the CPU mode register (see Figure 103). After CPU reprogramming mode control program is transferred to internal RAM, jump to this control program on RAM. (The following operations are controlled by this control program). Set "1" to the CPU reprogramming mode select bit. Apply VPPH to the CNVSS/VPP pin. Wait till CNVSS/VPP pin becomes 12V. Read the CPU reprogramming mode monitor flag to confirm whether the CPU reprogramming mode is valid. The operation of the flash memory is executed by software-command-writing to the flash command register . Note: The following are necessary other than this: *Control for data which is input from the external (serial I/O etc.) and to be programmed to the flash memory *Initial setting for ports etc. *Writing to the watchdog timer < Release procedure > Apply 0 V to the CNVSS/VPP pin. Wait till CNVSS/VPP pin becomes 0 V. Set the CPU reprogramming mode select bit to "0." Each software command is explained as follows. q Read command When "0016" is written to the flash command register, the 3803/ 3804 group enters the read mode. The contents of the corresponding address can be read by reading the flash memory (For instance, with the LDA instruction etc.) under this condition. The read mode is maintained until another command code is written to the flash command register. Accordingly, after setting the read mode once, the contents of the flash memory can continuously be read. After reset and after the reset command is executed, the read mode is set. b7 7 6 5 4 3 2 1 0 Flash command register (FCMD : address 0FFF16) Writing of software command b0 1 00 CPU mode register (CPUM : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : Not available 1 X : Not available Stack page selection bit 0 : 0 page 1 : 1 page Fix this bit to "1". Port XC switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function Main clock (XIN-XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bits b7 b6 0 0 : = f(XIN)/2 (high-speed mode) 0 1 : = f(XIN)/8 (middle-speed mode) 1 0 : = f(XCIN)/2 (low-speed mode) 1 1 : Not available Note: The flash command register is write-only register. Fig. 102 Flash command register bit configuration Fig. 103 CPU mode register bit configuration in CPU rewriting mode Rev.4.01 Nov 14, 2003 page 111 of 136 3803/3804 Group q Program command When "4016" is written to the flash command register, the 3803/ 3804 group enters the program mode. Subsequently to this, if the instruction (for instance, STA or LDM instruction) for writing byte data in the address to be programmed is executed, the control circuit of the flash memory executes the program. The erase/program busy flag of the flash memory control register is set to "1" when the program starts, and becomes "0" when the program is completed. Accordingly, after the write instruction is executed, CPU can recognize the completion of the program by polling this bit. The programmed area must be specified beforehand by the erase/ program area select bits. During programming, watchdog timer stops with "FFFF16" set. Note: A programming operation is not completed by executing the program command once. Always be sure to execute a program verify command after executing the program command. When the failure is found in this verification, the user must repeatedly execute the program command until the pass. Refer to Figure 104 for the flow chart of the programming. q Program verify command When "C016" is written to the flash command register, the 3803/ 3804 group enters the program verify mode. Subsequently to this, if the instruction (for instance, LDA instruction) for reading byte data from the address to be verified (i.e., previously programmed address), the contents which has been written to the address actually is read. CPU compares this read data with data which has been written by the previous program command. In consequence of the comparison, if not agreeing, the operation of "program program verify" must be executed again. q Erase command When writing "2016" twice continuously to the flash command register, the flash memory control circuit performs erase to the area specified beforehand by the erase/program area select bits. Erase/program busy flag of the flash memory control register becomes "1" when erase begins, and it becomes "0" when erase completes. Accordingly, CPU can recognize the completion of erase by polling this bit. Data "0016" must be written to all areas to be erased by the program and the program verify commands before the erase command is executed. During erasing, watchdog timer stops with "FFFF16" set. Note: The erasing operation is not completed by executing the erase command once. Always be sure to execute an erase verify command after executing the erase command. When the failure is found in this verification, the user must repeatedly execute the erase command until the pass. Refer to Figure 104 for the erasing flowchart. q Erase verify command When "A016" is written to the flash command register, the 3803/ 3804 group enters the erase verify mode. Subsequently to this, if the instruction (for instance, LDA instruction) for reading byte data from the address to be verified, the contents of the address is read. CPU must erase and verify to all erased areas in a unit of address. If the address of which data is not "FF16" (i.e., data is not erased) is found, it is necessary to discontinue erasure verification there, and execute the operation of "erase erase verify" again. Note: By executing the operation of "erase erase verify" again when the memory not erased is found. It is unnecessary to write data "0016" before erasing in this case. q Reset command The reset command is a command to discontinue the program or erase command on the way. When "FF16" is written to the command register two times continuously after "4016" or "2016" is written to the flash command register, the program, or erase command becomes invalid (reset), and the 3803/3804 group enters the reset mode. The contents of the memory does not change even if the reset command is executed. DC Electric Characteristics Note: The characteristic concerning the flash memory part are the same as the characteristic of the parallel I/O mode. AC Electric Characteristics Note: The characteristics are the same as the characteristic of the microcomputer mode. Rev.4.01 Nov 14, 2003 page 112 of 136 3803/3804 Group Program START Erase START ADRS = first location YES ALL BYTES = 0016 ? NO X=0 WRITE PROGRAM COMMAND WRITE PROGRAM DATA 4016 PROGRAM ALL BYTES = 0016 ADRS = first location DIN X=0 WAIT 1s WRITE ERASE COMMAND NO ERASE PROGRAM BUSY FLAG = 0 YES X=X+1 WRITE PROGRAM-VERIFY COMMAND DURATION = 6 s WRITE ERASE COMMAND 2016 2016 WAIT 1s C016 NO ERASE PROGRAM BUSY FLAG = 0 YES X=X+1 X = 25 ? NO FAIL YES WRITE ERASE-VERIFY COMMAND PASS DURATION = 6 s A016 VERIFY BYTE ? PASS VERIFY BYTE ? FAIL X = 1000 ? INC ADRS NO LAST ADRS ? NO YES WRITE READ COMMAND 0016 PASS DEVICE PASSED DEVICE FAILED NO INC ADRS LAST ADRS ? YES WRITE READ COMMAND FAIL YES PASS VERIFY BYTE ? VERIFY BYTE ? FAIL 0016 DEVICE PASSED DEVICE FAILED Fig. 104 Flowchart of program/erase operation at CPU reprogramming mode Rev.4.01 Nov 14, 2003 page 113 of 136 3803/3804 Group NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is "1." After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Serial I/O In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to "1." Serial I/O continues to output the final bit from the TXD pin after transmission is completed. SOUT2 pin for serial I/O2 goes to high impedance after transfer is completed. When in serial I/Os 1 and 3 (clock-synchronous mode) or in serial I/O2, an external clock is used as synchronous clock, write transmission data to the transmit buffer register or serial I/O2 register, during transfer clock is "H." Interrupts The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction. A-D Converter The comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(XIN) is at least on 500 kHz during an A-D conversion. Do not execute the STP instruction during an A-D conversion. Decimal Calculations * To calculate in decimal notation, set the decimal mode flag (D) to "1", then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. * In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. D-A Converter The accuracy of the D-A converter becomes rapidly poor under the VCC = 4.0 V or less condition; a supply voltage of VCC 4.0 V is recommended. When a D-A converter is not used, set all values of D-Ai conversion registers (i=1, 2) to "0016." Timers If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). Instruction Execution Time Multiplication and Division Instructions * The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. * The execution of these instructions does not change the contents of the processor status register. The instruction execution time is obtained by multiplying the period of the internal clock by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The period of the internal clock is double of the XIN period in high-speed mode. Ports The contents of the port direction registers cannot be read. The following cannot be used: * The data transfer instruction (LDA, etc.) * The operation instruction when the index X mode flag (T) is "1" * The instruction with the addressing mode which uses the value of a direction register as an index * The bit-test instruction (BBC or BBS, etc.) to a direction register * The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers. Rev.4.01 Nov 14, 2003 page 114 of 136 3803/3804 Group NOTES ON USAGE Handling of Power Source Pins In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (VCC pin) and GND pin (VSS pin), and between power source pin (VCC pin) and analog power source input pin (AVSS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 F-0.1 F is recommended. Flash Memory Version The CNVSS pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (VPP pin) as well. To improve the noise reduction, connect a track between CNVSS pin and VSS pin or VCC pin with 1 to 10 k resistance. The mask ROM version track of CNVSS pin has no operational interference even if it is connected to Vss pin or Vcc pin via a resistor. Electric Characteristic Differences Between Mask ROM and Flash Memory Version MCUs There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between Mask ROM and Flash Memory version MCUs due to the difference in the manufacturing processes. When manufacturing an application system with the Flash Memory version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial samples of the Mask ROM version. DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: 1.Mask ROM Confirmation Form 2.Mark Specification Form 3.Data to be written to ROM, in EPROM form (three identical copies) For the mask ROM confirmation and the mark specifications, ref e r t o t h e " R e n e s a s Te c h n o l o g y " H o m e p a g e ( h t t p : / / www.renesas.com/en/rom). Rev.4.01 Nov 14, 2003 page 115 of 136 3803/3804 Group ELECTRICAL CHARACTERISTICS Absolute maximum ratings Table 27 Absolute maximum ratings Symbol Parameter VCC Power source voltageS Input voltage P00-P07, P10-P17, P20-P27, VI P30, P31, P34-P37, P40-P47, P50-P57, P60-P67, VREF VI Input voltage P32, P33 VI Input voltage RESET, XIN VI Input voltage CNVSS (Mask ROM version) Input voltage CNVSS (Flash memory version) VI Output voltage P00-P07, P10-P17, P20-P27, VO P30, P31, P34-P37, P40-P47, P50-P57, P60-P67, XOUT VO Output voltage P32, P33 Pd Power dissipation Operating temperature Topr Storage temperature Tstg Note: In flat package, this value is 300 mW. Conditions Ratings -0.3 to 6.5 -0.3 to VCC +0.3 -0.3 to 5.8 -0.3 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to 13 -0.3 to VCC +0.3 -0.3 to 5.8 1000 (Note) -20 to 85 -65 to 125 Unit V V V V V V V V mW C C All voltages are based on VSS. Output transistors are cut off. Ta = 25 C Rev.4.01 Nov 14, 2003 page 116 of 136 3803/3804 Group Recommended operating conditions Table 28 Recommended operating conditions (VCC = 2.7 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) Symbol Power source voltage (Mask ROM version) Parameter f(XIN) 8.4 MHz f(XIN) 12.5 MHz f(XIN) 16.8 MHz f(XIN) 12.5 MHz f(XIN) 16.8 MHz Min. 2.7 4.0 4.5 4.0 4.5 2.0 2.7 0 AVSS 0.8VCC 0.8VCC 0.7VCC 1.4 0.8VCC 0 0 0 VCC VCC 5.5 5.5 5.5 VCC 0.2VCC 0.3VCC 0.6 0.2VCC 0.16VCC Limits Typ. 5.0 5.0 5.0 5.0 5.0 0 Max. 5.5 5.5 5.5 5.5 5.5 VCC VCC Unit VCC VCC VSS VREF AVSS VIA VIH VIH VIH VIH VIH VIL VIL VIL VIL VIL V Power source voltage (flash memory version) Power source voltage Analog reference voltage (when A-D converter is used) Analog reference voltage (when D-A converter is used) Analog power source voltage Analog input voltage AN0-AN15 "H" input voltage P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 "H" input voltage P32, P33 "H" input voltage (when I2C-BUS input level is selected) SDA, SCL "H" input voltage (when SMBUS input level is selected) SDA, SCL "H" input voltage RESET, XIN, XCIN, CNVSS "L" input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 "L" input voltage (when I2C-BUS input level is selected) SDA, SCL "L" input voltage (when SMBUS input level is selected) SDA, SCL "L" input voltage "L" input voltage RESET, CNVSS XIN, XCIN V V V V V V V V V V V V V V V V Rev.4.01 Nov 14, 2003 page 117 of 136 3803/3804 Group Table 29 Recommended operating conditions (VCC = 2.7 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) Symbol IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOL(avg) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) "H" total peak output current "H" total peak output current "L" total peak output current "L" total peak output current "L" total peak output current "H" total average output current "H" total average output current "L" total average output current "L" total average output current "L" total average output current "H" peak output current "L" peak output current "L" peak output current "H" average output current "L" average output current "L" average output current Main clock input oscillation frequency (Note 4) Parameter P00-P07, P10-P17, P20-P27, P30, P31, P34-P37 (Note 1) P40-P47, P50-P57, P60-P67 (Note 1) P00-P07, P10-P17, P30-P37 (Note 1) P20-P27 (Note 1) P40-P47,P50-P57, P60-P67 (Note 1) P00-P07, P10-P17, P20-P27, P30, P31, P34-P37 (Note 1) P40-P47,P50-P57, P60-P67 (Note 1) P00-P07, P10-P17, P30-P37 (Note 1) P20-P27 (Note 1) P40-P47,P50-P57, P60-P67 (Note 1) P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 (Note 2) P00-P07, P10-P17, P30-P37, P40-P47, P50-P57, P60-P67 (Note 2) P20-P27 (Note 2) P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 (Note 3) P00-P07, P10-P17, P30-P37, P40-P47, P50-P57, P60-P67 (Note 3) P20-P27 (Note 3) Vcc = 4.5-5.5 V Vcc = 4.0-4.5 V Vcc = 2.7-4.0 V 32.768 Limits Min. Typ. Max. -80 -80 80 80 80 -40 -40 40 40 40 -10 10 20 -5 5 10 16.8 8.6Vcc-21,9 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA MHz MHz MHz kHz f(XIN) f(XCIN) 3 41 Vcc- 26 13 Sub-clock input oscillation frequency (Notes 4, 5) 50 Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms. 4: When the oscillation frequency has a duty cycle of 50%. 5: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. Rev.4.01 Nov 14, 2003 page 118 of 136 3803/3804 Group Electrical characteristics Table 30 Electrical characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol Parameter "H" output voltage P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 (Note 1) "L" output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 Hysteresis CNTR0, CNTR1, CNTR2, INT0-INT4 Hysteresis RxD1, SCLK1, SIN2, SCLK2, RxD3, SCLK3 Hysteresis RESET VI = VCC (Pin floating. Pull-up transistors "off") VI = VCC VI = VCC VI = VSS (Pin floating. Pull-up transistors "off") VI = VSS VI = VSS VI = VSS VCC = 5.0 V VI = VSS VCC = 3.0 V When clock stopped -80 -30 2.0 -4 -210 -70 -420 -140 5.5 4 -5.0 -5.0 "H" input current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 "H" input current "H" input current RESET, CNVSS XIN Limits Test conditions IOH = -10 mA VCC = 4.0-5.5 V IOH = -1.0 mA VCC = 2.7-5.5 V IOL = 10 mA VCC = 4.0-5.5 V IOL = 1.6 mA VCC = 2.7-5.5 V 0.4 Min. VCC-2.0 VCC-1.0 2.0 0.4 Typ. Max. Unit V V V V V V V 5.0 5.0 A A A A A A A A V VOH VOL VT+-VT- VT+-VT- VT+-VT- IIH IIH IIH IIL IIL IIL IIL VRAM 0.5 0.5 "L" input current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 "L" input current "L" input current RESET,CNVSS XIN "L" input current (at Pull-up) P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 RAM hold voltage Note 1: P35 is measured when the P35/TxD3 P-channel output disable bit of the UART3 control register (bit 4 of address 003316) is "0". P45 is measured when the P45/TxD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is "0". Rev.4.01 Nov 14, 2003 page 119 of 136 3803/3804 Group Table 31 Electrical characteristics (flash memory version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol Limits Parameter Test conditions High-speed mode f(XIN) = 16.8 MHz f(XCIN) = 32.768 kHz Output transistors "off" High-speed mode f(XIN) = 12.5 MHz f(XCIN) = 32.768 kHz Output transistors "off" High-speed mode f(XIN) = 8.4 MHz f(XCIN) = 32.768 kHz Output transistors "off" High-speed mode f(XIN) = 16.8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors "off" Low-speed mode f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors "off" Low-speed mode f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors "off" Middle-speed mode f(XIN) = 16.8 MHz f(XCIN) = stopped Output transistors "off" Middle-speed mode f(XIN) = 16.8 MHz (in WIT state) f(XCIN) = stopped Output transistors "off" Increment when A-D conversion is executed f(XIN) = 16.8 MHz All oscillation stopped (in STP state) Output transistors "off" Ta = 25 C Ta = 85 C Min. Typ. 12 Max. 22 Unit mA 10 18 mA 7 13.5 mA 3.5 6 mA ICC Power source current 60 200 A 30 60 A 6 12 mA 3 5.5 mA 500 0.1 1.0 10 A A A Rev.4.01 Nov 14, 2003 page 120 of 136 3803/3804 Group Table 32 Electrical characteristics (mask ROM version) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Limits Symbol Parameter Test conditions High-speed mode f(XIN) = 16.8 MHz f(XCIN) = 32.768 kHz Output transistors "off" High-speed mode f(XIN) = 12.5 MHz f(XCIN) = 32.768 kHz Output transistors "off" High-speed mode f(XIN) = 8.4 MHz f(XCIN) = 32.768 kHz Output transistors "off" High-speed mode f(XIN) = 16.8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors "off" Low-speed mode f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors "off" Low-speed mode f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors "off" Low-speed mode (VCC = 3 V) f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors "off" Low-speed mode (VCC = 3 V) f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors "off" Middle-speed mode f(XIN) = 16.8 MHz f(XCIN) = stopped Output transistors "off" Middle-speed mode f(XIN) = 16.8 MHz (in WIT state) f(XCIN) = stopped Output transistors "off" Increment when A-D conversion is executed f(XIN) = 16.8 MHz All oscillation stopped (in STP state) Output transistors "off" Ta = 25 C Ta = 85 C Min. Typ. 8 Max. 15 Unit mA 6.5 12 mA 5 9 mA 2 3.6 mA 55 200 A 40 70 A ICC Power source current 15 40 A 8 15 A 4 7 mA 1.8 3.3 mA 500 0.1 1.0 10 A A A Rev.4.01 Nov 14, 2003 page 121 of 136 3803/3804 Group A-D converter characteristics Table 33 A-D converter characteristics (1) (VCC = 2.7 to 5.5 V, VREF = 2.0 V to VCC, VSS = AVSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) 10-bit A-D mode (when conversion mode selection bit (bit 7 of address 003816) is "0") Symbol - - tCONV RLADDER IVREF II(AD) Parameter Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current A-D port input current at A-D converter operated at A-D converter stopped VREF = 5.0 V VREF = 5.0 V 12 50 35 150 Test conditions Limits Min. Typ. Max. 10 VCC = VREF = 5.0 V 4 61 100 200 5 5.0 Unit bit LSB 2tc(XIN) k A A A Table 34 A-D converter characteristics (2) (VCC = 2.7 to 5.5 V, VREF = 2.0 V to VCC, VSS = AVSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) 8-bit A-D mode (when conversion mode selection bit (bit 7 of address 003816) is "1") Symbol - - tCONV RLADDER IVREF II(AD) Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current A-D port input current at A-D converter operated at A-D converter stopped VREF = 5.0 V VREF = 5.0 V 12 50 35 150 VCC = VREF = 5.0 V Parameter Test conditions Limits Min. Typ. Max. 8 2 50 100 200 5 5.0 Unit bit LSB 2tc(XIN) k A A A D-A converter characteristics Table 35 D-A converter characteristics (VCC = 2.7 to 5.5 V, VREF = 2.7 V to VCC, VSS = AVSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol - - tsu RO IVREF Resolution Absolute accuracy Setting time Output resistor Reference power source input current (Note 1) 4.0 VREF 5.5 V 2.7 VREF < 4.0 V 2 3.5 Parameter Test conditions Limits Min. Typ. Max. 8 1.0 2.5 3 5 3.2 Unit Bits % % s k mA Note 1: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being "0016". Rev.4.01 Nov 14, 2003 page 122 of 136 3803/3804 Group Timing requirements and switching characteristics Table 36 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) Main clock input cycle time (Vcc = 4.0-4.5 V) Main clock input "H" pulse width (Vcc = 4.5-5.5 V) tWH(XIN) Main clock input "H" pulse width (Vcc = 4.0-4.5 V) Main clock input "L" pulse width (Vcc = 4.5-5.5 V) tWL(XIN) tC(XCIN) tWH(XCIN) tWL(XCIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK1), tC(SCLK3) tWH(SCLK1), tWH(SCLK3) tWL(SCLK1), tWL(SCLK3) tsu(RxD1-SCLK1), tsu(RxD3-SCLK3) th(SCLK1-RxD1), th(SCLK3-RxD3) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SIN2-SCLK2) th(SCLK2-SIN2) Main clock input "L" pulse width (Vcc = 4.0-4.5 V) Sub-clock input cycle time Sub-clock input "H" pulse width Sub-clock input "L" pulse width CNTR0-CNTR2 input cycle time CNTR0-CNTR2 input "H" pulse width CNTR0-CNTR2 input "L" pulse width INT00, INT01, INT1, INT2, INT3, INT40, INT41 input "H" pulse width INT00, INT01, INT1, INT2, INT3, INT40, INT41 input "L" pulse width Serial I/O1, serial I/O3 clock input cycle time (Note) Serial I/O1, serial I/O3 clock input "H" pulse width (Note) Serial I/O1, serial I/O3 clock input "L" pulse width (Note) Serial I/O1, serial I/O3 input setup time Serial I/O1, serial I/O3 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 input setup time Serial I/O2 input hold time Reset input "L" pulse width Main clock input cycle time (Vcc = 4.5-5.5 V) Parameter Limits Min. 16 59.5 10000 86Vcc-219 25 4000 86Vcc-219 25 4000 86Vcc-219 20 5 5 200 80 80 80 80 800 370 370 220 100 1000 400 400 200 200 Typ. Max. Unit XIN cycle ns ns ns ns ns ns s s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note : When bit 6 of address 001A16 and bit 6 of address 003216 are "1" (clock synchronous). Divide this value by four when bit 6 of address 001A16 and bit 6 of address 003216 are "0" (UART). Rev.4.01 Nov 14, 2003 page 123 of 136 3803/3804 Group Table 37 Timing requirements (2) (VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(XCIN) tWH(XCIN) tWL(XCIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK1), tC(SCLK3) tWH(SCLK1), tWH(SCLK3) tWL(SCLK1), tWL(SCLK3) tsu(RxD1-SCLK1), tsu(RxD3-SCLK3) th(SCLK1-RxD1), th(SCLK3-RxD3) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SIN2-SCLK2) th(SCLK2-SIN2) Reset input "L" pulse width Main clock input cycle time Main clock input "H" pulse width Main clock input "L" pulse width Sub-clock input cycle time Sub-clock input "H" pulse width Sub-clock input "L" pulse width CNTR0-CNTR2 input cycle time CNTR0-CNTR2 input "H" pulse width CNTR0-CNTR2 input "L" pulse width INT00, INT01, INT1, INT2, INT3, INT40, INT41 input "H" pulse width INT00, INT01, INT1, INT2, INT3, INT40, INT41 input "L" pulse width Serial I/O1, serial I/O3 clock input cycle time (Note) Serial I/O1, serial I/O3 clock input "H" pulse width (Note) Serial I/O1, serial I/O3 clock input "L" pulse width (Note) Serial I/O1, serial I/O3 input setup time Serial I/O1, serial I/O3 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 input setup time Serial I/O2 input hold time Parameter Limits Min. 16 26 103 82Vcc-3 10000 82Vcc-3 10000 82Vcc-3 20 5 5 500 230 230 230 230 2000 950 950 400 200 2000 950 950 400 300 Typ. Max. Unit XIN cycle ns ns ns s s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note : When bit 6 of address 001A16 is "1" (clock synchronous). Divide this value by four when bit 6 of address 001A16 is "0" (UART). Rev.4.01 Nov 14, 2003 page 124 of 136 3803/3804 Group Table 38 Switching characteristics 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tWH (SCLK1), tWH (SCLK3) tWL (SCLK1), tWL (SCLK3) td (SCLK1-TXD1) , td (SCLK3-TXD3) tv (SCLK1-TXD1) , tv (SCLK3-TXD3) Parameter Serial I/O1, serial I/O3 clock output "H" pulse width Serial I/O1, serial I/O3 clock output "L" pulse width Serial I/O1, serial I/O3 output delay time (Note 1) Serial I/O1, serial I/O3 output valid time (Note 1) Fig. 105 tC(SCLK2)/2-160 tC(SCLK2)/2-160 200 0 30 10 10 30 30 -30 30 30 Test conditions Limits Min. tC(SCLK1)/2-30 tC(SCLK3)/2-30 tC(SCLK1)/2-30 tC(SCLK3)/2-30 140 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns tr (SCLK1) , tr (SCLK3) Serial I/O1, serial I/O3 clock output rising time tf (SCLK1), tf (SCLK3) Serial I/O1, serial I/O3 clock output falling time tWH (SCLK2) tWL (SCLK2) td (SCLK2-SOUT2) tV (SCLK2-SOUT2) tf (SCLK2) tr (CMOS) tf (CMOS) Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Notes 1: When the P45/TXD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is "0". When the P35/TXD3 P-channel output disable bit of the UART3 control register (bit 4 of address 003316) is "0". 2: The XOUT pin is excluded. Table 39 Switching characteristics 2 (VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tWH (SCLK1), tWH (SCLK3) tWL (SCLK1), tWL (SCLK3) td (SCLK1-TXD1) , td (SCLK3-TXD3) tv (SCLK1-TXD1) , tv (SCLK3-TXD3) Parameter Serial I/O1, serial I/O3 clock output "H" pulse width Serial I/O1, serial I/O3 clock output "L" pulse width Serial I/O1, serial I/O3 output delay time (Note 1) Serial I/O1, serial I/O3 output valid time (Note 1) Fig. 105 tC(SCLK2)/2-240 tC(SCLK2)/2-240 400 0 50 20 20 50 50 -30 50 50 Test conditions Limits Min. tC(SCLK1)/2-50 tC(SCLK3)/2-50 tC(SCLK1)/2-50 tC(SCLK3)/2-50 350 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns tr (SCLK1) , tr (SCLK3) Serial I/O1, serial I/O3 clock output rising time tf (SCLK1), tf (SCLK3) Serial I/O1, serial I/O3 clock output falling time tWH (SCLK2) tWL (SCLK2) td (SCLK2-SOUT2) tV (SCLK2-SOUT2) tf (SCLK2) tr (CMOS) tf (CMOS) Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Notes 1: When the P45/TXD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is "0". When the P35/TXD3 P-channel output disable bit of the UART3 control register (bit 4 of address 003316) is "0". 2: The XOUT pin is excluded. Rev.4.01 Nov 14, 2003 page 125 of 136 3803/3804 Group 1k Measurement output pin 100pF Measurement output pin 100pF CMOS output N-channel open-drain output Fig. 105 Circuit for measuring output switching characteristics (1) Fig. 106 Circuit for measuring output switching characteristics (2) Rev.4.01 Nov 14, 2003 page 126 of 136 3803/3804 Group Timing diagram in single-chip mode tC(CNTR) tWH(CNTR) tWL(CNTR) 0.2VCC CNTR0, CNTR1, CNTR2 0.8VCC INT1, INT2, INT3 INT00, INT40 INT01, INT41 tWH(INT) 0.8VCC 0.2VCC tWL(INT) tW(RESET) RESET 0.2VCC 0.8VCC tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC XIN 0.8VCC tC(XCIN) tWH(XCIN) tWL(XCIN) 0.2VCC XCIN 0.8VCC tC(SCLK1), tC(SCLK2), tC(SCLK3) tf tWL(SCLK1), tWL(SCLK2), tWL(SCLK3) tr tWH(SCLK1), tWH(SCLK2), tWH(SCLK3) SCLK1 SCLK2 SCLK3 RXD1 RXD3 SIN2 TXD1 TXD3 SOUT2 Fig. 107 Timing diagram (in single-chip mode) 0.2VCC tsu(RxD1-SCLK1), tsu(SIN2-SCLK2), tsu(RxD3-SCLK3) 0.8VCC 0.2VCC 0.8VCC th(SCLK1-RxD1), th(SCLK2-SIN2), th(SCLK3-RxD3) td(SCLK1-TXD1),td(SCLK2-SOUT2),td(SCLK3-TXD3) tv(SCLK1-TXD1), tv(SCLK2-SOUT2), tv(SCLK3-TXD3) Rev.4.01 Nov 14, 2003 page 127 of 136 3803/3804 Group Table 40 Multi-master I2C-BUS bus line characteristics Standard clock mode High-speed clock mode Symbol tBUF tHD;STA tLOW tR tHD;DAT tHIGH tF tSU;DAT tSU;STA tSU;STO Bus free time Hold time for START condition Hold time for SCL clock = "0" Rising time of both SCL and SDA signals Data hold time Hold time for SCL clock = "1" Falling time of both SCL and SDA signals Data setup time Setup time for repeated START condition Setup time for STOP condition 250 4.7 4.0 0 4.0 300 Parameter Min. 4.7 4.0 4.7 1000 Max. Min. 1.3 0.6 1.3 20+0.1Cb 0 0.6 20+0.1Cb 100 0.6 0.6 300 300 0.9 Max. Unit s s s ns s s ns ns s s Note: Cb = total capacitance of 1 bus line SDA tBUF tLOW tR tF Sr P tHD:STA tsu:STO SCL P S tHD:STA tHD:DAT tHIGH tsu:DAT tsu:STA S : START condition Sr: RESTART condition P : STOP condition Fig. 108 Timing diagram of multi-master I2C-BUS Rev.4.01 Nov 14, 2003 page 128 of 136 3803/3804 Group PACKAGE OUTLINE 64P6N-A Plastic 64pin 1414mm body QFP JEDEC Code - HD D b2 EIAJ Package Code QFP64-P-1414-0.80 Weight(g) 1.11 Lead Material Alloy 42 e MD 64 49 1 48 I2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 y b2 I2 MD ME Dimension in Millimeters Max Nom Min - 3.05 - 0.2 0.1 0 - - 2.8 0.45 0.35 0.3 0.2 0.15 0.13 14.2 14.0 13.8 14.2 14.0 13.8 - 0.8 - 17.1 16.8 16.5 17.1 16.8 16.5 0.8 0.6 0.4 1.4 - - - 0.1 - - 10 0 - 0.5 - - - 1.3 - 14.6 - - 14.6 - HE E 16 33 17 32 A L1 A2 F A1 e y b L Detail F 64P6Q-A MMP JEDEC Code - Weight(g) - Lead Material Cu Alloy c Plastic 64pin 1010mm body LQFP MD e EIAJ Package Code LQFP64-P-1010-0.50 ME b2 I2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 Lp A3 A3 HD D 64 49 1 48 16 33 17 32 A e F L1 A1 y b x y b2 I2 MD ME x M L Detail F Lp Dimension in Millimeters Min Nom Max - - 1.7 0.1 0.2 0 - - 1.4 0.13 0.18 0.28 0.105 0.125 0.175 9.9 10.0 10.1 9.9 10.0 10.1 - 0.5 - 11.8 12.0 12.2 11.8 12.0 12.2 0.3 0.5 0.7 1.0 - - 0.45 0.6 0.75 - 0.25 - - - 0.08 - - 0.1 - 0 10 - - 0.225 1.0 - - - - 10.4 - - 10.4 HE E A2 Rev.4.01 Nov 14, 2003 page 129 of 136 c ME 3803/3804 Group 64P4B EIAJ Package Code SDIP64-P-750-1.78 JEDEC Code - Weight(g) 7.9 Lead Material Alloy 42 Plastic 64pin 750mil SDIP 64 33 1 32 Symbol D A2 e SEATING PLANE b1 b b2 A A1 A2 b b1 b2 c D E e e1 L Dimension in Millimeters Max Nom Min 5.08 - - - - 0.38 - 3.8 - 0.6 0.5 0.4 1.3 1.0 0.9 1.05 0.75 0.65 0.32 0.25 0.2 56.6 56.4 56.2 17.15 17.0 16.85 - 1.778 - - 19.05 - - - 2.8 15 - 0 L A Rev.4.01 Nov 14, 2003 page 130 of 136 A1 e1 E c REVISION HISTORY Rev. 0.1 Date Page 03/15/99 3803/3804 GROUP DATA SHEET Description Summary First Edition; Only including overview The issue including all information will be released in April. Functional descriptions are added. All pages 9 10 34 52 60 63 66 "PRELIMINARY Notice: This is..." eliminated. Product names are added into Figure 8. Product names are added into Table 3. Explanation of "Timer divider" of "8-bit Timers" is revised. Explanation of Note 7 is revised. Explanation of Note 7 is revised. Explanation of "A-D CONVERTER" is revised. Explanations of Figure 56 are partly revised. Explanations of "Watchdog Timer Initial Value" and "Watchdog Timer Operations" are revised. Explanations of Figure 60 are partly revised. Explanation of "MULTI-MASTER I2C-BUS INTERFACE" is revised. Explanation of Note eliminated. Explanations of Figure 62 are partly revised. Explanations of "I2C Data Shift Register" and "I2C Address Registers 0 to 2" are revised. Explanation of Bit 5 of "I2C Clock Control Register" is revised. Value of "Setup time" and "Hold time" into Table 13 are revised. Explanation of Bit 5 of "I2C Special Mode Status Register" is added. Note is added into Figure 73. Explanation of Bit 1 of "I2C Special Mode Control Register" is added. Explanation of Bit 6 of "I2C Special Mode Control Register" is revised. Note is added into Figure 74. Register Contents of (21) into Figure 78 is revised. Explanations of Figure 82 are partly revised. Note 2 into Figure 82 is revised. Table 28 is revised for only flash memory version. Table 29 is added. "qMinimum instruction execution time" of "FEATURES" is revised. "qMemory size" of "FEATURES" is revised. " 1.0 2.0 05/25/99 09/09/99 67 68 69 75 76 77 82 86 117 3.0 06/28/00 1 1 1 1 9 11-13 14 (1/5) REVISION HISTORY Rev. 3.0 Date Page 06/28/00 21 22 24 25 37 37 37 37 37 37 37 37 37 37 38 38 38 38 38 38 39 42 42 42 43 3803/3804 GROUP DATA SHEET Description Summary (7) into Figure 16 is partly revised. (14) into Figure 17 is partly revised. (7) into Figure 19 is partly revised. (14) into Figure 20 is partly revised. Explanations of "Timer divider" are partly eliminated. "qPrescaler 12" is added. Explanations of "Timer 1 and Timer 2" are partly eliminated. "Prescaler X and prescaler Y" is added. Explanations of "Timer X and Timer Y" are partly eliminated. Explanations of "qMode selection" and "qExplanation of operation" of "(1) Timer mode" of "Timer X and Timer Y" are partly eliminated. "qCount source selection" and "qInterrupt" of "(1) Timer mode" of "Timer X and Timer Y" are eliminated. "qCount source selection" and "qInterrupt" of "(2) Pulse output mode" of "Timer X and Timer Y" are eliminated. Explanations of "qExplanation of operation" of "(2) Pulse output mode" of "Timer X and Timer Y" are partly added. Explanations of "sPrecautions" of "(2) Pulse output mode" of "Timer X and Timer Y" are partly eliminated. Explanations of "qMode selection" and "qExplanation of operation" of "(3) Event counter mode" of "Timer X and Timer Y" are revised. "qInterrupt" of "(3) Event counter mode" of "Timer X and Timer Y" are eliminated. "sPrecautions" of "(3) Event counter mode" of "Timer X and Timer Y" are added. "qCount source selection" of "(4) Pulse width measurement mode" of "Timer X and Timer Y" are eliminated. Explanations of "qExplanation of operation" of "(4) Pulse width measurement mode" of "Timer X and Timer Y" are partly eliminated. Explanations of "sPrecautions" of "(4) Pulse width measurement mode" of "Timer X and Timer Y" are revised. Bit name into Figure 29 is partly added. Explanations of "qMode selection" of "(1) Timer mode" of "q16-bit Timers" are partly added. Explanations of "qExplanation of operation" of "(1) Timer mode" of "q16-bit Timers" are partly eliminated. Explanations of "qMode selection" of "(3) Pulse output mode" of "q16-bit Timers" are partly added. Explanations of "qMode selection" of "(4) Pulse period measurement mode" of "q16-bit Timers" are partly added. (2/5) REVISION HISTORY Rev. 3.0 Date Page 06/28/00 43 44 44 45 46 55 63 68 70 71 74 75 78 78 79 79 80 80 80 80 84 110 111 114 121 122 123 123 3803/3804 GROUP DATA SHEET Description Summary Explanations of "qMode selection" of "(5) Pulse width measurement mode" of "q16-bit Timers" are partly added. Explanations of "qMode selection" of "(6) Programmable waveform generating mode" of "q16-bit Timers" are partly added. Explanations of "qMode selection" of "(7) Programmable one-shot generating mode" of "q16-bit Timers" are partly added. Figure 32 is partly revised. Note into Figure 33 is added. Explanations of "7. Transmit interrupt request when transmit enable bit is set" are revised. Explanations of "7. Transmit interrupt request when transmit enable bit is set" are revised. Explanations of "D-A CONVERTER" are partly eliminated. Figure 64 is partly revised. Explanations of "[I2C Slave Address Registers 0 to 2 (S0D0 to S0D2)]" are partly added. Explanations of "*Bit 3: Arbitration lost detecting flag (AL)" of "[I2C Status Register (S1)]" are partly added. Explanations of "*Bit 7: Communication mode specification bit (master/slave specification bit: MST)" of "[I2C Status Register (S1)]" are partly revised. "*Bit 7: Data receive mode at Stop/Low-speed mode bit (STR)" of "[I2C START/STOP Condition Control Register (S2D)]" is eliminated. Explanations of b7 into Figure 74 are revised. "*Bit 4: Time out flag (TIOUT)" of "[I2C Special Mode Status Register (S3)]" is eliminated. Figure 75 is partly revised. "*Bit 0: I2C time out control bit (TOEN)" is eliminated. "*Bit 4: Time out flag clear bit (TOFCL)" is eliminated. Figure 76 is partly revised. Note into Figure 76 is added. Explanations of "RESET CIRCUIT" are partly revised. Explanations of "Functional Outline (CPU reprogramming mode)" of "(3) Flash memory mode 3 (CPU reprogramming mode)" are partly eliminated. Explanations of b3, b1, b0 into Figure 103 are partly revised. Explanations of "Instruction Execution Time" are partly reviesd. Table 31 is partly eliminated. Limits of RO into Table 34 are revised. Limits and unit of tw(RESET) into Table 35 are revised. Symbol of th(SCLK3-RxD3) into Table 35 is revised. (3/5) REVISION HISTORY Rev. 3.0 4.0 Date Page 06/28/00 05/15/02 124 125 9 15 21 22 23 24 25 26 31 42 43 43 44 54 54 55 56 62 62 63 70 71 76 77 78 83 87 87 89 91 91 93 94 95 95 96 97 97 98 3803/3804 GROUP DATA SHEET Description Summary Limits and unit of tw(RESET) into Table 36 are revised. Limits of tWH(SCLK1), tWH(SCLK3) into Tables 37 and 38 are partly added. Figure 8 is partly revised. Sub-sub clause name of "qMiddle-speed mode automatic switch by program" is partly eliminated. Figure 16 is partly revised. Figure 17 is partly revised. Figure 18 is partly revised. Figure 19 is partly revised. Figure 20 is partly revised. Figure 21 is partly revised. Explanations of "sNotes" are revised. Explanations of "q16-bit Timers" are partly revised. Explanations of "qExplanation of operation" of "(4) Pulse period measurement mode" are revised. Explanations of "qExplanation of operation" of "(5) Pulse width measurement mode" are revised. Explanations of "qExplanation of operation" of "(7) Programmable one-shot generating mode" are partly revised. Explanations of "qNote" of "2.1 Stop of transmission operation" are partly added. Explanations of "qNote 1 (only transmission operation is stopped)" of "2.3 Stop of transmit/receive operation" are partly added. Explanations of "5. Data transmission control with referring to transmit shift register completion flag" are partly added. Figure 46 is partly revised. Explanations of "qNote" of "2.1 Stop of transmission operation" are partly added. Explanations of "qNote 1 (only transmission operation is stopped)" of "2.2 Stop of transmit/receive operation" are partly added. Explanations of "5. Data transmission control with referring to transmit shift register completion flag" are partly added. Explanations of "MULTI-MASTER I2C-BUS INTERFACE" are partly revised. Explanations of "[I2C Data Shift Register (S0)]" are partly revised. Explanations of "START Condition Generating Method" are partly revised. Table 14 is partly revised. Table 15 is partly revised. Explanations of "2" of "(2) Start condition generating procedure using multi-master" are partly revised. Explanations of "CLOCK GENERATING CIRCUIT" are partly revised. Explanations of "sNote" of "(2) Wait mode" are partly added. Figure 84 is partly revised. Explanations of "(1) Flash memory mode 1 (parallel I/O mode)" are partly revised. Table 16 is partly revised. Figure 86 is partly revised. Figure 87 is partly revised. Explanations of "Read-only Mode" are partly revised. Explanations of "Read/Write Mode" are partly revised. Explanations of "qRead command" are partly revised. Explanations of "qProgram command" are partly revised. Explanations of "qProgram verify command" are partly revised. Explanations of "qErase verify command" are partly revised. (4/5) REVISION HISTORY Rev. 4.0 Date 05/15/02 Page 101 101 101 101 102 103 115 115 116 117 117 129 4.01 Nov. 14, 2003 6 7 13 19 20 31 73 87 89 93 94 102 103 122 3803/3804 GROUP DATA SHEET Description Summary Limits of tRC into Table 21 are revised. Limits of ta(AD) into Table 21 are revised. Limits of ta(CE) into Table 21 are revised. Limits of ta(OE) into Table 21 are revised. Figure 93 is partly revised. Figure 94 is partly revised. "Electric Characteristic Differences Between Mask ROM and Flash Memory Version MCUs" is added. Explanations of "DATA REQUIRED FOR MASK ORDERS" are partly added. Explanations of "Note" into Table 27 are partly revised. VCC into Table 28 are partly added. Parameter of VIH into Table 28 is partly revised. 64P6Q-A package outline is partly revised. Table 1 is partly revised. Table 2 is partly revised. Explanations of "[Processor status register (PS)]" are partly revised. Table 6 is partly revised. Table 7 is partly revised. Explanations of "sNotes" are partly revised. Figure 67 is partly revised. Explanations of "(2) Wait mode" is partly revised. Figure 84 is partly revised. Figure 86 is partly revised. Figure 87 is partly revised. Figure 93 is partly revised. Figure 94 is partly revised. Table 35 is partly revised. (5/5) Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. http://www.renesas.com (c) 2003. Renesas Technology Corp., All rights reserved. Printed in Japan. |
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